Abstract: Systems and methods for managing a redundant management module are provided. In this regard, a representative system, among others, includes first and second management modules that are configured to manage a computing device; and a programmable logic device that is configured to: instruct the first management module to manage the computing device responsive to detecting that the first management module is ready to manage the computing device, and instruct the second management module to manage the computing device responsive to detecting that the first management module failed to manage the computing device.

Abstract: Systems and methods for managing a redundant management module are provided. In this regard, a representative system, among others, includes first and second management modules that are configured to manage a computing device; and a programmable logic device that is configured to: instruct the first management module to manage the computing device responsive to detecting that the first management module is ready to manage the computing device, and instruct the second management module to manage the computing device responsive to detecting that the first management module failed to manage the computing device.

Abstract: Embodiments of the invention provide a method and apparatus for automatically evaluating and allocating resources in a cell based system. In one method embodiment, the present invention receives a request to generate a cell based system of resources. A list of allocatable resources having corresponding evaluation data is then accessed. The request for the cell based system is then compared with the list of allocatable resources having corresponding evaluation data. The allocatable resources are then assigned to the cell based system.

Abstract: A microprocessor includes a plurality of execution units of a same type, and a first register operable to select between a first and a second mode of operation, wherein the microprocessor utilizes at least one of the execution units as a redundant execution unit during the first mode of operation and utilizes none of the execution units as a redundant execution unit during the second mode of operation.

Abstract: A processor can write its state to an external state cache. Thus, in the event of a processor failure, the stored state can be read and assumed, either by the original processor or another processor. Thus, a process can be resumed from the stored state rather than reconstructed from initial conditions.

Abstract: A computer system has redundant I/O interface modules for managing communications between an incorporating computer system and an external system such as a network or multi-port disk array. A redundant I/O interface manager directs communications through one of the redundant I/O interface modules, and switches the communications through the other, e.g., when a failure of the first I/O interface module is detected or predicted. The redundant I/O interface module appears to the operating system of the incorporating system as the first I/O interface module would so the switching is effectively invisible to the operating system.

Abstract: Methodology, systems and media associated with selectively allocating memory are described. One exemplary method embodiment comprises receiving a quality data that identifies the quality of one or more allocatable subsets of a memory and selectively allocating a subset of memory from the allocatable memory to an application based, at least in part, on memory quality as identified in the quality data.

Abstract: A computer system comprising an operating system, a first component that comprises a first test module, a second component that comprises a second test module, and an interconnect coupling the first component and the second component is provided. The first test module is configured to provide a first test pattern to the second test module on the interconnect in response to a first signal from the operating system.

Abstract: A computer system that includes a processor, a first bus coupled to the processor, a memory controller coupled to the first bus, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the first bus, and a test module coupled to the first I/O controller is provided. The test module is configured to cause tests to be performed on the memory using the first bus.

Abstract: A method and corresponding apparatus for detecting and rejecting high impedance failures in chip interconnects use monitoring circuitry on a chip to provide accurate and pro-active prediction of interconnect failures. The apparatus may include a resistance continuity monitoring circuit (RCMC), and a signal path connecting a representative set of pins to the RCMC. The RCMC measures the resistance of a connection of the representative set of pins with a circuit board during system operation and outputs a measured resistance data. The apparatus further includes additional analog-to-digital (A/D) hardware to perform an analog to digital conversion of the measured resistance data. Additional on-chip circuitry and/or microcode may be used to perform an algorithm on the digital resistance data to generate an interconnect status signal. For example, the method may output a failure signal when the measured resistance data exceeds a threshold resistance value.

Abstract: A computer system that includes a processor, a memory controller coupled to the processor, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the memory controller, a first expansion slot coupled to the first I/O controller, and a test module card coupled to the first expansion slot wherein the test module card is configured to cause tests to be performed on the memory using direct memory access (DMA) is provided.

Abstract: One embodiment disclosed relates to a method of executing program code on a target microprocessor with multiple CPU cores thereon. One of the CPU cores is selected for testing, and inter-core context switching is performed. Parallel execution occurs of diagnostic code on the selected CPU core and the program code on remaining CPU cores. Another embodiment disclosed relates to a microprocessor having a plurality of CPU cores integrated on the microprocessor chip. Inter-core communications circuitry is coupled to each of the CPU cores and configured to perform context switching between the CPU cores.

Abstract: A computer system comprising a processor configured to cause an operating system to be booted, a test module, and a component coupled to the test module and configured to receive a clock input is provided. The test module is configured to cause the clock input to be provided to the component at a first frequency, and the test module is configured to cause a first test to be performed on the component subsequent to the clock input being provided to the component at the first frequency and the operating system being booted.

Abstract: A computer system comprising a first processor that is configured to cause an operating system to be booted, a test module, a component coupled to the test module, and a power supply coupled to the test module and the component is provided. The test module is configured to provide a first signal to the power supply to cause a first voltage to be provided to the component, and the test module is configured to cause a first test to be performed on the component subsequent to the first voltage being provided to the component and the operating system being booted.

Abstract: A computer system comprising a system module, a test module, a first cell, and a second cell is provided. The system module is configured to cause the test module to test the first cell subsequent to the second cell being allocated to a first instance of an operating system.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of program code and diagnostics code. The diagnostic code is scheduled to be executed on the selected execution unit. The program code is scheduled to be executed on remaining execution units of the same type.

Abstract: An example memory quality assuring system is provided. The system may include a memory mapping logic configured to facilitate accessing memory locations and redirecting memory accessing operations. The system may also include a memory quality assurance logic configured to logically replace a first memory location with a second memory location, to initiate testing logically isolated memory locations, and to selectively logically remove tested memory locations based on the testing. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the application. It is submitted with the understanding that it will not be employed to interpret or limit the scope or meaning of the claims 37 CFR 1.72(b).

Abstract: An example memory scrubbing logic is provided. The logic may be operably connectable to a main memory and a processor. The memory access logic may include a memory for mirroring a main memory location and a logic for scrubbing the main memory location.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple functional units of a same type. The method includes opportunistically scheduling a redundant operation on one of the functional units that would otherwise be idle during a cycle.