Abstract: One embodiment disclosed relates to a method of providing CPU functional testing. Operations are executed on multiple functional units of a same type in the CPU. The outputs of the multiple functional units are automatically compared. The results of the comparison are checked only for redundant operations. Another embodiment disclosed relates to a microprocessor with built-in functional testing capability. The microprocessor includes multiple functional units of a same type and registers that receive outputs from the multiple functional units. In addition, comparator circuitry is built-in that also receives the outputs from the multiple functional units and compares the outputs to provide functional testing.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor. A cycle is identified during which a functional unit would otherwise be idle. A diagnostic operation is opportunistically scheduled for execution on the functional unit during that cycle, and a comparison is scheduled to compare a result from executing the diagnostic operation with a corresponding predetermined result.

Abstract: A computer system comprising a processor, a memory, and a memory controller coupled to the processor and the memory is provided. The memory controller comprises a first cache and a cache control. The cache control is configured to cause a portion of the memory to be copied into the first cache. The cache control is configured to cause first information to be provided from the first cache to the processor in response to receiving a read transaction from the processor that includes an address in the portion of memory during testing of the portion.

Abstract: An example memory error ranking system is provided. The system may include an error detector logic that detects memory errors and a ranking logic that ranks the quality of a memory location based on memory errors detected by the error detector logic.

Abstract: One embodiment disclosed pertains to a printed circuit assembly (PCA) with built-in circuitry to test integrated circuit (IC) connector loading. The PCA includes at least the IC connector to be tested, an indicator circuit, and a power circuit. The IC connector is configured to interconnect to a packaged IC. The indicator circuit is coupled to the IC connector. Proper seating of the packaged IC in the IC connector is determined and indicated by the indicator circuit. The power circuit provides power to the indicator circuit.

Abstract: A printed circuit board comprises a conductive layer and a via transecting the conductive layer. The printed circuit board comprises a pattern of conductive material having a plurality of voids in the conductive layer near the via.

Abstract: A printed circuit board comprises a first conductive plane and a second conductive plane substantially parallel to the first conductive plane. The printed circuit board comprises a via signal barrel transecting the first and second conductive planes and a first anti-pad positioned between the first conductive plane and the via signal barrel. The first anti-pad has a first voided area. The printed circuit board comprises a second anti-pad positioned between the second conductive plane and the via signal barrel. The second anti-pad has a second voided area. The first voided area does not completely overlap the second voided area.

Abstract: One embodiment disclosed relates to a microprocessor for targeted fault-tolerant computing. The microprocessor's decode circuitry is configured to decode a fault-tolerant version of an instruction and a non-fault-tolerant version of the instruction distinctly from each other. The microprocessor's execution circuitry is configured to execute the fault-tolerant version of the instruction with redundancy checking and to execute the non-fault-tolerant version of the instruction without redundancy checking.