Patents by Inventor Damodar R. Thummalapally
Damodar R. Thummalapally has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8541824Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: GrantFiled: July 19, 2012Date of Patent: September 24, 2013Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Publication number: 20130020638Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: ApplicationFiled: September 14, 2012Publication date: January 24, 2013Applicant: SUVOLTA, INC.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Publication number: 20130020639Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: ApplicationFiled: September 14, 2012Publication date: January 24, 2013Applicant: Suvolta, IncInventors: Scott E. Thompson, Damodar R. Thummalapally
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Publication number: 20120299111Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.Type: ApplicationFiled: July 19, 2012Publication date: November 29, 2012Applicant: SUVOLTA, INC.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Patent number: 8273617Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.Type: GrantFiled: February 18, 2010Date of Patent: September 25, 2012Assignee: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Patent number: 7969759Abstract: A memory cell includes a first access transistor, first and second pull-up transistors, a depletion transistor, and first and second pull-down transistors. The first access transistor is connected to a word line and connected between a first bit line and a first data node. The first pull-up transistor is connected to a first power supply point and the second pull-up transistor is connected to the first power supply point and the second data node. The first pull-down transistor is connected to a second power supply point and to the first data node and the second pull-down transistor is connected to the depletion transistor and to the second data node. The depletion transistor is connected to the word line and to the second power supply point.Type: GrantFiled: December 19, 2008Date of Patent: June 28, 2011Assignee: SuVolta, Inc.Inventors: Damodar R. Thummalapally, Richard K. Chou
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Patent number: 7943971Abstract: A junction field effect transistor (JFET) can include a top gate structure and an active semiconductor region. The active semiconductor region can include a side surface and a top surface formed below the top gate structure. The active semiconductor region can also include a channel region formed below the top gate structure, a bottom gate region formed below the channel region, and a gate tie region formed on the side surface that makes an electrical connection between the top gate structure and the bottom gate region.Type: GrantFiled: December 17, 2008Date of Patent: May 17, 2011Assignee: SuVolta, Inc.Inventors: Ashok K. Kapoor, Damodar R. Thummalapally
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Publication number: 20110074498Abstract: A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors.Type: ApplicationFiled: February 18, 2010Publication date: March 31, 2011Applicant: SuVolta, Inc.Inventors: Scott E. Thompson, Damodar R. Thummalapally
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Patent number: 7847354Abstract: A semiconductor device comprises a partially depleted semiconductor-on-insulator structure having both a three terminal JFET and a four terminal JFET constructed thereon. The four terminal JFET comprises a source region, a drain region, a channel region, a front gate region, and a back gate region formed in a semiconductor layer of the partially depleted semiconductor-on-insulator structure. The three terminal JFET comprises a source region formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure, and a drain region spaced apart from the source region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure. The three terminal JFET further comprises a channel region between the source region and the drain region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure.Type: GrantFiled: February 6, 2009Date of Patent: December 7, 2010Assignee: SuVolta, Inc.Inventor: Damodar R. Thummalapally
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Patent number: 7848130Abstract: A memory cell includes an access transistor, first and second pull-up transistors, first and second pull-down transistors, and a first search transistor. The access transistor is connected to a first word line and connected between a first bit line and a first data node. The first pull-up transistor is connected to a first power supply point and the first data node, and the second pull-up transistor is connected to the first power supply point and the second data node. The first pull-down transistor is connected to a second power supply point and the first data node, and the second pull-down transistor is connected to the second power supply point and the second data node. The first search transistor is connected to the second data node and includes a source terminal connected to a third power supply point comprising a voltage less than the voltage at the second power supply point.Type: GrantFiled: December 19, 2008Date of Patent: December 7, 2010Assignee: SuVolta, Inc.Inventors: Damodar R. Thummalapally, Richard K. Chou
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Patent number: 7843721Abstract: A memory device including a static random access memory (SRAM) cell comprising junction field effect transistors (JFETs) has been disclosed. The memory cell includes a first bipolar junction transistor (BJT) for driving a bit line at logic levels having a potential outside the potential range in which the SRAM cell operates. An amplifier including a level translator circuit provides a level shifting operation on the data provided by the bit line to provide level shifted data having a voltage swing within the potential range in which the SRAM cell operates. The level translator circuit includes a second BJT. In this way, fast read operation of a SRAM cell comprising JFETs may be provided.Type: GrantFiled: September 18, 2008Date of Patent: November 30, 2010Assignee: SuVolta, Inc.Inventors: Richard K. Chou, Damodar R. Thummalapally
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Patent number: 7746146Abstract: A level shifting circuit can include a first input junction field effect transistor (JFET) having a gate coupled to receive an input signal having a first voltage swing that provides a controllable impedance path between a first supply node and a first terminal of a first bias stack including at least one JFET. A driver circuit can be coupled to receive an output from the first bias stack that provides a level shifted output having a second voltage swing that is less than the first voltage swing.Type: GrantFiled: September 1, 2006Date of Patent: June 29, 2010Assignee: SuVolta, Inc.Inventors: Richard K. Chou, Damodar R. Thummalapally
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Patent number: 7729149Abstract: A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell and can be used to form a CAM cell. The CAM cell may be a ternary CAM cell formed with as few as two JFETs.Type: GrantFiled: May 1, 2007Date of Patent: June 1, 2010Assignee: SuVolta, Inc.Inventor: Damodar R. Thummalapally
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Patent number: 7694069Abstract: A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted.Type: GrantFiled: March 29, 2007Date of Patent: April 6, 2010Assignee: DSM Solutions, Inc.Inventor: Damodar R. Thummalapally
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Patent number: 7646233Abstract: A level shifting circuit can include a first driver junction field effect transistor (JFET) having a source coupled to a reference supply node and a second driver JFET of a second conductivity type having a source coupled to a boosted supply node, and a first charge pump circuit. The first charge pump circuit can be coupled between the first driver control node and an input node coupled to receive an input signal, and can couple a first terminal of a first capacitor between a reference supply node and a power supply node in response to an input signal. The power supply node can be coupled to receive a power supply potential, the reference supply node can be coupled to receive a reference potential, and the boosted power supply node can be coupled to receive a boosted potential. The reference potential can be between the power supply potential and the boosted potential.Type: GrantFiled: July 28, 2006Date of Patent: January 12, 2010Assignee: DSM Solutions, Inc.Inventors: Damodar R. Thummalapally, Richard K. Chou
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Patent number: 7633784Abstract: A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion comprising p-channel junction field effect transistors. The TCAM cell including an x-cell, y-cell, and comparator circuit. The x-cell, y-cell, and comparator circuits comprising p-channel JFETs.Type: GrantFiled: May 17, 2007Date of Patent: December 15, 2009Assignee: DSM Solutions, Inc.Inventor: Damodar R. Thummalapally
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Patent number: 7629812Abstract: A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region.Type: GrantFiled: August 3, 2007Date of Patent: December 8, 2009Assignee: DSM Solutions, Inc.Inventors: Damodar R. Thummalapally, Abhijit Ray
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Static random access memory having cells with junction field effect and bipolar junction transistors
Publication number: 20090168508Abstract: A static random access memory (SRAM) device can include at least one SRAM cell having storage section that includes at least a first junction field effect transistor (JFET) with a gate terminal formed from a semiconductor layer deposited on a substrate surface. The storage section can also include at least a first storage node that provides a potential corresponding to a stored data value. The SRAM cell further includes a first access section that includes at least a first bipolar junction transistor (BJT) having an emitter formed from the semiconductor layer.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: Ashok K. Kapoor, Damodar R. Thummalapally, Abhijit Ray -
Publication number: 20090033361Abstract: A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region.Type: ApplicationFiled: August 3, 2007Publication date: February 5, 2009Inventors: Damodar R. Thummalapally, Abhijit Ray
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Publication number: 20080285322Abstract: A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion comprising p-channel junction field effect transistors. The TCAM cell including an x-cell, y-cell, and comparator circuit. The x-cell, y-cell, and comparator circuits comprising p-channel JFETs.Type: ApplicationFiled: May 17, 2007Publication date: November 20, 2008Inventor: Damodar R. Thummalapally