Abstract: A passgate circuit comprises a first depletion mode n-channel JFET, a depletion mode p-channel JFET, and a second depletion mode n-channel JFET. The first depletion mode n-channel JFET has a first terminal coupled to an input port, a second terminal that receives a first control signal, and a third terminal. The depletion mode p-channel JFET has a first terminal coupled to the third terminal of the first depletion mode n-channel JFET, a second terminal that receives a second control signal, and a third terminal. The second depletion mode n-channel JFET has a first terminal coupled to the third terminal of the depletion mode p-channel JFET, a second terminal that receives the first control signal, and a third terminal coupled to an output port.

Abstract: A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell.

Abstract: A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell and can be used to form a CAM cell. The CAM cell may be a ternary CAM cell formed with as few as two JFETs.

Abstract: A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted.

Abstract: A level shifting circuit can include a first input junction field effect transistor (JFET) having a gate coupled to receive an input signal having a first voltage swing that provides a controllable impedance path between a first supply node and a first terminal of a first bias stack including at least one JFET. A driver circuit can be coupled to receive an output from the first bias stack that provides a level shifted output having a second voltage swing that is less than the first voltage swing.

Abstract: A level shifting circuit can include a first driver junction field effect transistor (JFET) of a first conductivity type having a source coupled to a first supply node, a drain coupled to an output node, and a gate coupled to a first driver control node. A first driver control circuit can include a first control JFET of a second conductivity type having a source coupled to a second supply node, a gate coupled to an input node that is coupled to receive an input signal, and a first level shifting stack coupled between the source of the first control JFET and the first driver control node. The magnitude of the potential between the first supply node and the second supply node is greater than a voltage swing of the input signal.

Abstract: A semiconductor device can include a first circuit section having at least one transistor coupled to at least three conductive lines formed from a conductive layer. No more than one of the at least one of the three conductive lines forms a control terminal of the at least one transistor. In addition, a second circuit section includes at least two transistors. Each such transistor can have a control terminal formed by a conductive line formed from the same conductive layer. The three conductive lines of the first circuit section can have the same pitch pattern as the conductive lines of the second circuit section.

Abstract: A level shifting circuit can include a first driver junction field effect transistor (JFET) having a source coupled to a reference supply node and a second driver JFET of a second conductivity type having a source coupled to a boosted supply node, and a first charge pump circuit. The first charge pump circuit can be coupled between the first driver control node and an input node coupled to receive an input signal, and can couple a first terminal of a first capacitor between a reference supply node and a power supply node in response to an input signal. The power supply node can be coupled to receive a power supply potential, the reference supply node can be coupled to receive a reference potential, and the boosted power supply node can be coupled to receive a boosted potential. The reference potential can be between the power supply potential and the boosted potential.

Abstract: A method of protecting data received on a client device while coupled to a network through a communication channel has been disclosed. A client device (130) may receive protected data through a communication channel (140). A user public key (320) and a user private key (410) may be received by the client device (130). When protected data is to be stored on permanent storage (640), a link to a hidden file (220) may be generated using a random number generator. The link may be encrypted using user public key (320) to generate an encrypted link. Protected data may be stored in hidden file (220) and the encrypted link may be stored in a shield file (210). When the protected data is read from permanent storage (640), the encrypted link may be decrypted using user private key (410) to generate the link identifying hidden file (220). User private key (410) may not be stored on permanent storage (640).