Abstract: A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

Abstract: A transistor structure is provided which includes a graphene layer located on an insulating layer, a first metal portion overlying a portion of the graphene layer, a second metal portion contacting and overhanging the first metal portion, a first electrode contacting a portion of the graphene layer and laterally offset from a first sidewall of the first metal portion by a lateral spacing, and a second electrode contacting another portion of the graphene layer and laterally offset from a second sidewall of the first metal portion by the lateral spacing.

Abstract: A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode.

Abstract: A method of forming a transistor structure is provided. The method includes forming a graphene layer on an insulating layer; forming a stack of a first metal portion and a second metal portion over the graphene layer, wherein sidewalls of the first metal portion are vertically coincident with sidewalls of the second metal portion; and laterally offsetting the sidewalls of the first metal portion relative to the sidewalls of the second metal portion by a lateral distance.

Abstract: A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide.

Abstract: The invention provides a method for molecular analysis. In the method, sidewalls are formed extending through a structure between two structure surfaces, to define an aperture. A layer of material is deposited on the aperture sidewalls and the two structure surfaces. The aperture with the deposited material layer is then configured in a liquid solution with a gradient in a chemical potential, between the two structure surfaces defining the aperture, that is sufficient to cause molecular translocation through the aperture.

Abstract: There are provided methods for functionalizing a planar surface of a microelectronic structure, by exposing the surface to at least one vapor including at least one functionalization species, such as NO2 or CH3ONO, that non-covalently bonds to the surface while providing a functionalization layer of chemically functional groups, to produce a functionalized surface. The functionalized surface is exposed to at least one vapor stabilization species that reacts with the functionalization layer to form a stabilization layer that stabilizes the functionalization layer against desorption from the planar microelectronic surface while providing chemically functional groups. The stabilized surface is exposed to at least one material layer precursor species that deposits a material layer on the stabilized planar microelectronic surface. The stabilized planar microelectronic surface can be annealed at a peak annealing temperature that is less than about 700° C.

Abstract: A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode.

Abstract: The invention provides methods functionalizing a planar surface of a graphene layer, a graphite surface, or microelectronic structure. The graphene layer, graphite surface, or planar microelectronic structure surface is exposed to at least one vapor including at least one functionalization species that non-covalently bonds to the graphene layer, a graphite surface, or planar microelectronic surface while providing a functionalization layer of chemically functional groups, to produce a functionalized graphene layer, graphite surface, or planar microelectronic surface.

Abstract: Semiconductor structures and electronic devices are provided that includes at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material.

Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.

Abstract: A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.

Abstract: A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide.

Abstract: The invention provides methods functionalizing a planar surface of a graphene layer, a graphite surface, or microelectronic structure. The graphene layer, graphite surface, or planar microelectronic structure surface is exposed to at least one vapor including at least one functionalization species that non-covalently bonds to the graphene layer, a graphite surface, or planar microelectronic surface while providing a functionalization layer of chemically functional groups, to produce a functionalized graphene layer, graphite surface, or planar microelectronic surface.

Abstract: In a method for functionalizing a carbon nanotube surface, the nanotube surface is exposed to at least one vapor including at least one functionalization species that non-covalently bonds to the nanotube surface, providing chemically functional groups at the nanotube surface, producing a functionalized nanotube surface. A functionalized nanotube surface can be exposed to at least one vapor stabilization species that reacts with the functionalization layer to form a stabilization layer that stabilizes the functionalization layer against desorption from the nanotube surface while providing chemically functional groups at the nanotube surface, producing a stabilized nanotube surface. The stabilized nanotube surface can be exposed to at least one material layer precursor species that deposits a material layer on the stabilized nanotube surface.

Abstract: In a method for functionalizing a carbon nanotube surface, the nanotube surface is exposed to at least one vapor including at least one functionalization species that non-covalently bonds to the nanotube surface, providing chemically functional groups at the nanotube surface, producing a functionalized nanotube surface. A functionalized nanotube surface can be exposed to at least one vapor stabilization species that reacts with the functionalization layer to form a stabilization layer that stabilizes the functionalization layer against desorption from the nanotube surface while providing chemically functional groups at the nanotube surface, producing a stabilized nanotube surface. The stabilized nanotube surface can be exposed to at least one material layer precursor species that deposits a material layer on the stabilized nanotube surface.

Abstract: In a method for functionalizing a carbon nanotube surface, the nanotube surface is exposed to at least one vapor including at least one functionalization species that non-covalently bonds to the nanotube surface, providing chemically functional groups at the nanotube surface, producing a functionalized nanotube surface. A functionalized nanotube surface can be exposed to at least one vapor stabilization species that reacts with the functionalization layer to form a stabilization layer that stabilizes the functionalization layer against desorption from the nanotube surface while providing chemically functional groups at the nanotube surface, producing a stabilized nanotube surface. The stabilized nanotube surface can be exposed to at least one material layer precursor species that deposits a material layer on the stabilized nanotube surface.