Abstract: A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region.

Abstract: Vertical NROM devices are made in a substantially single crystalline silicon substrate having a planar surface. The vertical NROM cell and device has a first region and a second region spaced apart from one another by a channel. A dieletric is spaced apart from the channel to capture charges injected from the channel onto the dielectric. A gate is positioned over the dielectric and spaced apart therefrom and controls the flow of current through the channel. In the improvement of the present invention, a portion of the channel is substantially perpendicular to the top planar surface of the substrate. Methods for making the vertical NROM cell and array are also disclosed.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates. A second region is formed between adjacent, spaced apart, control gates.

Abstract: A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates to form connected control gates. A second region is formed between adjacent, spaced apart, control gates.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates to form connected control gates. A second region is formed between adjacent, spaced apart, control gates.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates. A second region is formed between adjacent, spaced apart, control gates.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates. A second region is formed between adjacent, spaced apart, control gates.

Abstract: In an environment of competitive local and interexchange carriers, offering number portability between local carriers serving a common region and between switches serving that region, each local carrier accesses a regional database to determine the identity of the carrier and switch serving a local customer. In addition, interexchange carriers access a national database to determine the identity of the carrier and switch serving the customer specified by the number dialed by an originating customer. For customers requiring high reliability service, alternate carriers can be used to serve such customers in case the primary carrier is unavailable; the databases identify these alternate carriers. Advantageously, this arrangement allows a high degree of freedom of movement of customers between carriers and geographic relocation without requiring a number change.

Abstract: In accordance with the teachings of a prior application, in a telecommunications network, a local database stores destination telephone number information derived from a more global database, shared by a plurality of switching systems usually remote from all or most of the systems. One or more bit maps are used to store key indicators for each telephone number for which information may be required. This invention relates to a method and apparatus for automatically updating the local database, by recognizing that a switch identified as serving a directory number does not have access to the line corresponding to that number; when this condition is discovered, the global database is increased and the local database updated.

Abstract: A full programmable and erasable non-volatile floating gate memory array uses an array of memory cells arranged in a plurality of rows and columns. Each cell is of the type with a first region, a spaced apart second region and a channel region in between. A floating gate is disposed over and is insulated from a portion of the channel region and the second region. An electrically conductive gate has a first section disposed over and insulated from the first region and is disposed and is adjacent to the floating gate and is insulated therefrom and has a second section disposed over the floating gate and is insulated therefrom. The cells are arranged in rows with the second region for connection to a common line. The control gate of each of the memory cells is for connecting to a word line associated with the row. Each column is connected to the first region of the memory cells arranged in the column.

Abstract: In a telecommunications network, a method and apparatus for decreasing access time of information normally stored in a data base, shared by a plurality of switching systems usually remote from all or most of the systems. One or more bit maps are used to store key indicators for each telephone number for which information may be required. In one specific embodiment, a bit map indicates whether the information is stored locally in the switch, so that an access to the remote database is not required. In another embodiment, a bit map stores an indication of whether the desired information is a default attribute, or one of a plurality of common attributes of the information being sought. Advantageously, the number of data accesses required of the remote data base is sharply reduced, thus reducing the average call set up time.

Abstract: In an environment of competitive local and interexchange carriers, offering number portability between local carriers-serving a common region and between switches serving that region, each local carrier accesses a regional database to determine the identify of the carrier and switch serving a local customer. In addition, interexchange carriers access a national database to determine the identity of the carrier and switch serving the customer specified by the number dialed by an originating customer. For customers requiring high reliability service, alternate carriers can be used to serve such customers in case the primary carrier is unavailable; the databases identify these alternate carriers. Advantageously, this arrangement allows a high degree of freedom of movement of customers between carriers and geographic relocation without requiring a number change.

Abstract: A device for producing variable colors from projected white light and quantifying the color changes resulting therefrom is provided which is useful in color-styling designs and color shade matching. The device comprises (1) an adjustable color filter having at least two primary-color areas upon which a portion of said projected white light is incident, (2) light-attenuation means which attenuates the quantity of light transmitted from (by attenuating either the incident white light or transmitted color light) each of the primary-color areas as well as the portion of the projected light which is transmitted unfiltered, and (3) control means comprising (a) a light-measuring unit for measuring the transmitted light and generating a signal proportional to the amount of light measured, (b) means responsive to said signal to determine the quantity of each component of transmitted light present and (c) means responsive to (b) for controlling each of the light-attenuation means.

Abstract: An electron spectrometer including a high pass filter, an electron multiplier and a reflection chamber is improved by placing a planar grid in the reflection chamber between the high pass filter and the electron multiplier.