Patents by Inventor Dana Lee

Dana Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flash memory with targeted read scrub algorithm
    Patent number: 9053808
    Abstract: A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: June 9, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Steven T. Sprouse, Alexandra Bauche, Yichao Huang, Jian Chen, Jianmin Huang, Dana Lee
  • Defect or program disturb detection with full data recovery capability
    Patent number: 9053810
    Abstract: A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 9, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepanshu Dutta, Dana Lee, Yan Li, Grishma Shah, Farookh Moogat, Masaaki Higashitani
  • Erased state reading
    Patent number: 9047974
    Abstract: A method of determining whether a page of NAND flash memory cells is in an erased condition includes applying a first set of read conditions to identify a first number of cells having threshold voltages above a discrimination voltage under the first set of read conditions, if the first number of cells is less than a first predetermined number, applying a second set of read conditions that is different from the first set of read conditions to identify a second number of cells having threshold voltages above the discrimination voltage under the second set of read conditions, and if the second number of cells exceeds a second predetermined number, marking the page of flash memory cells as partially programmed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 2, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Jianmin Huang, Zhenming Zhou, Gautam Ashok Dusija, Chris Nga Yee Avila, Dana Lee
  • On chip dynamic read level scan and error detection for nonvolatile storage
    Patent number: 9036417
    Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 19, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Wenzhou Chen, Zhenming Zhou, Jun Wan, Deepanshu Dutta, Yi-Chieh Chen, Dana Lee
  • Identification and Operation of Sub-Prime Blocks in Nonvolatile Memory
    Publication number: 20150134885
    Abstract: In a block-erasable nonvolatile memory array, blocks are categorized as bad blocks, prime blocks, and sub-prime blocks. Sub-prime blocks are identified from their proximity to bad blocks or from testing. Sub-prime blocks are configured for limited operation (e.g. only storing non-critical data, or data copied elsewhere, or using some additional or enhanced redundancy scheme).
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: SanDisk Technologies Inc.
    Inventors: Chun Sum Yeung, Jian Chen, Aaron Lee, Abhijeet Manohar, Chris Avila, Dana Lee, Jianmin Huang
  • ADAPTIVE INITIAL PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY
    Publication number: 20150131380
    Abstract: When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Henry Chin, Dana Lee
  • Adaptive initial program voltage for non-volatile memory
    Patent number: 8971128
    Abstract: When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: March 3, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Henry Chin, Dana Lee
  • DATA RECOVERY FROM BLOCKS WITH GATE SHORTS
    Publication number: 20150058698
    Abstract: A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Inventors: Dana Lee, Abhijeet Manohar
  • Block level grading for reliability and yield improvement
    Patent number: 8953398
    Abstract: A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 10, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Jianmin Huang, Mrinal Kochar, Ashish Ghai
  • NON-VOLATILE MEMORY AND METHOD WITH PEAK CURRENT CONTROL
    Publication number: 20150023116
    Abstract: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Dana Lee, Yi-Chieh Chen, Farookh Moogat
  • WORD LINE DEFECT DETECTION AND HANDLING FOR A DATA STORAGE DEVICE
    Publication number: 20150006976
    Abstract: A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory and circuitry associated with operation of memory cells of the 3D memory. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.
    Type: Application
    Filed: May 22, 2014
    Publication date: January 1, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: SEUNGJUNE JEON, IDAN ALROD, ERAN SHARON, DANA LEE
  • WORD LINE DEFECT DETECTION AND HANDLING FOR A DATA STORAGE DEVICE
    Publication number: 20150006975
    Abstract: A data storage device includes a non-volatile memory and a controller. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: SEUNGJUNE JEON, IDAN ALROD, ERAN SHARON, DANA LEE
  • Systems and methods for lower page writes
    Patent number: 8902652
    Abstract: In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: December 2, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Jianmin Huang, Bo Lei, Jun Wan, Gerrit Jan Hemink, Steven T. Sprouse, Dana Lee
  • INTERNAL DATA LOAD FOR NON-VOLATILE STORAGE
    Publication number: 20140347925
    Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Inventors: Wenzhou Chen, Dana Lee, Zhenming Zhou, Guirong Liang
  • Split Gate NAND Flash Memory Structure And Array, Method Of Programming, Erasing And Reading Thereof, And Method Of Manufacturing
    Publication number: 20140340967
    Abstract: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
    Type: Application
    Filed: June 27, 2014
    Publication date: November 20, 2014
    Inventors: Yuniarto Widjaja, John W. Cooksey, Changyuan Chen, Feng Gao, Ya-Fen Lin, Dana Lee
  • Erased page confirmation in multilevel memory
    Patent number: 8887011
    Abstract: In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: November 11, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Ting Luo, Jianmin Huang, Chris Nga Yee Avila, Dana Lee, Gautam Ashok Dusija
  • Simultaneous sensing of multiple wordlines and detection of NAND failures
    Patent number: 8873288
    Abstract: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: October 28, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Eran Sharon, Yan Li, Dana Lee, Idan Alrod
  • Internal data load for non-volatile storage
    Patent number: 8861269
    Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: October 14, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Wenzhou Chen, Dana Lee, Zhenming Zhou, Guirong Liang
  • Non-volatile memory and method with peak current control
    Patent number: 8854900
    Abstract: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: October 7, 2014
    Assignee: SanDisk Technologies, Inc.
    Inventors: Dana Lee, Yi-Chieh Chen, Farookh Moogat
  • INTERNAL DATA LOAD FOR NON-VOLATILE STORAGE
    Publication number: 20140254262
    Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Wenzhou Chen, Dana Lee, Zhenming Zhou, Guirong Liang