Patents by Inventor Dana Lee

Dana Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SIMULTANEOUS SENSING OF MULTIPLE WORDLINES AND DETECTION OF NAND FAILURES
    Publication number: 20140254272
    Abstract: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.
    Type: Application
    Filed: April 21, 2014
    Publication date: September 11, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Eran Sharon, Yan Li, Dana Lee, Idan Alrod
  • Defect Or Program Disturb Detection With Full Data Recovery Capability
    Publication number: 20140254264
    Abstract: A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Deepanshu Dutta, Dana Lee, Yan Li, Grishma Shah, Farookh Moogat, Masaaki Higashitani
  • P-type control gate in non-volatile storage
    Patent number: 8803220
    Abstract: Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: August 12, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Takashi Whitney Orimoto, Atsushi Suyama, Ming Tian, Henry Chin, Henry Chien, Vinod Robert Purayath, Dana Lee
  • ADAPTIVE INITIAL PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY
    Publication number: 20140215128
    Abstract: When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: SANDISK TECHNOLOGIES, INC.
    Inventors: Henry Chin, Dana Lee
  • Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
    Patent number: 8780642
    Abstract: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: July 15, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Yuniarto Widjaja, John W. Cooksey, Changyuan Chen, Feng Gao, Ya-Fen Lin, Dana Lee
  • Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures
    Patent number: 8750042
    Abstract: Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 10, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Eran Sharon, Yan Li, Dana Lee, Idan Alrod
  • Read compensation for partially programmed blocks of non-volatile storage
    Patent number: 8743615
    Abstract: Read compensation for partially programmed blocks of non-volatile storage is provided. In partially programmed blocks, the threshold voltage distributions may be shifted down relative to their final positions. Upon receiving a request to read a page that is stored in a block, a determination may be made whether the block is partially programmed. If so, then a suitable compensation may be made when reading the requested page. This compensation may compensate for the non-volatile storage elements (or pages) in the block that have not yet been programmed. The amount of compensation may be based on the amount of interference that would be caused to the requested page by later programming of the other pages. The compensation may compensate for shifts in threshold voltage distributions of the requested page that would occur from later programming of other pages.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: June 3, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Ken Oowada
  • Erased State Reading
    Publication number: 20140098610
    Abstract: Memory cells that are indicated as being erased but are suspected of being partially programmed may be subject to a verification scheme that first performs a conventional read and then, if the conventional read does not indicate partial programming, performs a second read using lower read-pass voltage on at least one neighboring word line.
    Type: Application
    Filed: March 1, 2013
    Publication date: April 10, 2014
    Applicant: SanDisk Technologies Inc
    Inventors: Jianmin Huang, Zhenming Zhou, Gautam Ashok Dusija, Chris Nga Yee Avila, Dana Lee
  • Scrub techniques for use with dynamic read
    Patent number: 8687421
    Abstract: The decision on whether to refresh or retire a memory block is based on the set of dynamic read values being used. In a memory system using a table of dynamic read values, the table is configured to include how to handle read error (retire, refresh) in addition to the read parameters for the different dynamic read cases. In a refinement, the read case number can used to prioritize blocks selected for refresh or retire. In cases where the read scrub is to be made more precise, multiple dynamic read cases can be applied. Further, which cases are applied can be intelligently selected.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 1, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Chris Avila, Jianmin Huang, Dana Lee
  • Erased Page Confirmation in Multilevel Memory
    Publication number: 20140075252
    Abstract: In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition.
    Type: Application
    Filed: March 4, 2013
    Publication date: March 13, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Ting Luo, Jianmin Huang, Chris Nga Yee Avila, Dana Lee, Gautam Ashok Dusija
  • ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE
    Publication number: 20140063940
    Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.
    Type: Application
    Filed: February 7, 2013
    Publication date: March 6, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Wenzhou Chen, Zhenming Zhou, Jun Wan, Deepanshu Dutta, Yi-Chieh Chen, Dana Lee
  • DEVICE BASED WEAR LEVELING
    Publication number: 20140040681
    Abstract: A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Jonathan Wolfman, Dana Lee, Jonathan Hsu
  • Ramping pass voltage to enhance channel boost in memory device
    Patent number: 8644075
    Abstract: In a non-volatile storage system, first and second substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. The first and second substrate channel regions are created on either side of an isolation word line. During a program pulse time period in which a program pulse is applied to a selected word line, a voltage applied to an unselected word line which extends directly over the second channel region is stepped up to a respective pre-program pulse voltage, at a faster rate at which a voltage applied to an unselected word line which extends directly over the first channel region is stepped up to a respective pre-program pulse voltage. This helps improve the isolation between the channel regions.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: February 4, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Gerrit Jan Hemink, Shih-Chung Lee, Anubhav Khandelwal, Henry Chin, Guirong Liang, Dana Lee
  • Non-Volatile Memory and Method with Peak Current Control
    Publication number: 20140029357
    Abstract: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Inventors: Dana Lee, Yi-Chieh Chen, Farookh Moogat
  • P-TYPE CONTROL GATE IN NON-VOLATILE STORAGE
    Publication number: 20130341700
    Abstract: Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.
    Type: Application
    Filed: August 23, 2013
    Publication date: December 26, 2013
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Takashi Whitney Orimoto, Atsushi Suyama, Ming Tian, Henry Chin, Henry Chien, Vinod Robert Purayath, Dana Lee
  • FLASH MEMORY WITH TARGETED READ SCRUB ALGORITHM
    Publication number: 20130346805
    Abstract: A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Inventors: Steven T. Sprouse, Alexandra Bauche, Yichao Huang, Jian Chen, Jianmin Huang, Dana Lee
  • Offset non-volatile storage
    Patent number: 8614915
    Abstract: A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: December 24, 2013
    Assignee: Sandisk Technologies Inc.
    Inventors: Jeffrey W. Lutze, Dana Lee
  • BLOCK LEVEL GRADING FOR RELIABILITY AND YIELD IMPROVEMENT
    Publication number: 20130336059
    Abstract: A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Dana Lee, Jianmin Huang, Mrinal Kochar, Ashish Ghai
  • Ramping Pass Voltage To Enhance Channel Boost In Memory Device
    Publication number: 20130314987
    Abstract: In a non-volatile storage system, first and second substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. The first and second substrate channel regions are created on either side of an isolation word line. During a program pulse time period in which a program pulse is applied to a selected word line, a voltage applied to an unselected word line which extends directly over the second channel region is stepped up to a respective pre-program pulse voltage, at a faster rate at which a voltage applied to an unselected word line which extends directly over the first channel region is stepped up to a respective pre-program pulse voltage. This helps improve the isolation between the channel regions.
    Type: Application
    Filed: July 31, 2013
    Publication date: November 28, 2013
    Applicant: SanDisk Technologies Inc.
    Inventors: Gerrit Jan Hemink, Shih-Chung Lee, Anubhav Khandelwal, Henry Chin, Guirong Liang, Dana Lee
  • On chip dynamic read for non-volatile storage
    Patent number: 8576624
    Abstract: Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: November 5, 2013
    Assignee: SanDisk Technologies, Inc.
    Inventors: Deepanshu Dutta, Dana Lee, Jeffrey Lutze