Patents by Inventor Daniel B. Aubertine

Daniel B. Aubertine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879241
    Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 29, 2020
    Assignee: INTEL Corporation
    Inventors: Glenn A. Glass, Prashant Majhi, Anand S. Murthy, Tahir Ghani, Daniel B. Aubertine, Heidi M. Meyer, Karthik Jambunathan, Gopinath Bhimarasetti
  • Patent number: 10559689
    Abstract: Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jacob M. Jensen, Daniel B. Aubertine, Chandra S. Mohapatra
  • Patent number: 10403626
    Abstract: Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: September 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi
  • Patent number: 10396203
    Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi
  • Patent number: 10373977
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: August 6, 2019
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Chandra S. Mohapatra, Karthik Jambunathan, Gilbert Dewey, Willy Rachmady
  • Publication number: 20190006508
    Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.
    Type: Application
    Filed: May 30, 2018
    Publication date: January 3, 2019
    Inventors: Glenn A. GLASS, Anand S. MURTHY, Daniel B. AUBERTINE, Subhash M. JOSHI
  • Publication number: 20180374951
    Abstract: Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.
    Type: Application
    Filed: December 24, 2015
    Publication date: December 27, 2018
    Applicant: INTEL CORPORATION
    Inventors: KARTHIK JAMBUNATHAN, GLENN A. GLASS, ANAND S. MURTHY, JACOB M. JENSEN, DANIEL B. AUBERTINE, CHANDRA S. MOHAPATRA
  • Patent number: 10084087
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand S. Murthy, Hemant V. Deshpande, Daniel B. Aubertine
  • Publication number: 20180247939
    Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 30, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, PRASHANT MAJHI, ANAND S. MURTHY, TAHIR GHANI, DANIEL B. AUBERTINE, HEIDI M. MEYER, KARTHIK JAMBUNATHAN, GOPINATH BHIMARASETTI
  • Patent number: 10014412
    Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi
  • Publication number: 20180158841
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 7, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, DANIEL B. AUBERTINE, TAHIR GHANI, JACK T. KAVALIEROS, BENJAMIN CHU-KUNG, CHANDRA S. MOHAPATRA, KARTHIK JAMBUNATHAN, GILBERT DEWEY, WILLY RACHMADY
  • Patent number: 9893149
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: February 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
  • Publication number: 20180019170
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Application
    Filed: August 3, 2017
    Publication date: January 18, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, DANIEL B. AUBERTINE, ANAND S. MURTHY, GAURAV THAREJA, TAHIR GHANI
  • Patent number: 9812524
    Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: November 7, 2017
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine
  • Patent number: 9728464
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: August 8, 2017
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Tahir Ghani
  • Publication number: 20170222052
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Applicant: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand S. Murthy, Hemant V. Deshpande, Daniel B. Aubertine
  • Publication number: 20170222035
    Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 3, 2017
    Inventors: Glenn A. GLASS, Anand S. MURTHY, Daniel B. AUBERTINE, Subhash M. JOSHI
  • Patent number: 9660078
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Patent number: 9653584
    Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi
  • Publication number: 20170133376
    Abstract: Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).
    Type: Application
    Filed: March 24, 2014
    Publication date: May 11, 2017
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, DANIEL B. AUBERTINE, SUBHASH M. JOSHI