Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for determining extremum numerical values. Numerical values may be stored in files of a stack, with each bit of the numerical value stored in a content addressable memory (CAM) cell of the file. Each file may be associated with an accumulator circuit, which provides an accumulator signal. An extremum search operation may be performed where a sequence of comparison bits are compared in a bit-by-bit fashion to each bit of the numerical values. The accumulator circuits each provide an accumulator signal which indicates if the numerical value in the associated file is an extremum value or not. Examples of extremum search operations include finding a maximum of the numerical values and a minimum of the numerical values.

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

Abstract: An apparatus may include multiple memory devices. Each memory device may include multiple memory banks. Addresses of accessed word lines for a particular portion of memory and the number of times those word lines are accessed may be tracked by each memory device. When a memory device determines that an accessed word line is an aggressor word line, the memory device alerts other memory devices of the apparatus. The memory devices may then perform targeted refresh operations on victim word lines of the aggressor word line.

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

Abstract: The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and a controller. The controller is configured to perform a first operation beginning at a first address to transfer data from the array of memory cells to the cache, and perform a second operation concurrently with the first operation, the second operation beginning at a second address.

Abstract: Systems and methods are provided that provide protection from undesired latching that may be caused by indeterminate interamble periods in an input/output data strobe (DQS) signal. Interamble compensation circuitry selectively filters out interamble states of the DQS signal to reduce provision of interamble signals to downstream components that use the DQS signal to identify data latching times.

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.

Abstract: Addresses of accessed word lines are stored. Data related to victim word lines associated with the accessed word line are also stored. The victim word lines may have data stored in relation to multiple accessed word lines. The data related to the victim word lines is adjusted when the victim word line is refreshed during a targeted refresh operation or an auto-refresh operation. The data related to the victim word lines is adjusted when the victim word line is accessed during a memory access operation.

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Abstract: Apparatuses and methods for memory array accessibility can include an apparatus with an array of memory cells. The array can include a first portion accessible by a controller of the array and inaccessible to devices external to the apparatus. The array can include a second portion accessible to the devices external to the apparatus. The array can include a number of registers that store row address that indicate which portion of the array is the first portion. The apparatus can include the controller configured to access the number of registers to allow access to the second portion by the devices external to the apparatus based on the stored row addresses.

Abstract: Memory devices receive a data signal and an accompanying data strobing signal, which informs the device that data is ready for latching. The data strobing signal enables capturing the data while the data signal transitions from a logic high to a logic low or vice versa, resulting in an indeterminate output (e.g., between 0 and 1). The indeterminate value may cause metastability in memory operations using the indeterminate output. To prevent or reduce metastability, a cascaded timing arbiter latch includes cascaded alternating NAND timing arbiters and NOR timing arbiters. In some embodiments, these logic gates are connected to transistors above and below the cascaded timing arbiters. The cascaded timing arbiters and/or transistors provide amplification on a feedback path of the latch. In other embodiments, the cascaded timing arbiters are isolated by inverters and are not connected to transistors. This embodiment reduces capacitive loading on nodes of the internal feedback path.

Abstract: A memory device includes a command interface configured to receive a write command and internal write adjust (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based upon the received write command and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture a data signal (DQ) using the IWS.

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.