Patents by Inventor Daniel B. Penney

Daniel B. Penney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • APPARATUSES AND METHODS TO SELECTIVELY PERFORM LOGICAL OPERATIONS
    Publication number: 20190362759
    Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Inventors: Daniel B. Penney, Harish N. Venkata
  • WRITE LEVEL ARBITER CIRCUITRY
    Publication number: 20190362770
    Abstract: Devices and methods include utilizing memory including a group of storage elements, such as memory banks. A command interface is configured to receive a write command to write data to the memory. A data strobe is received to assist in writing the data to the memory. Phase division circuitry is configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory. Arbiter circuitry is configured to detect which phase of the plurality of phases captures a write start signal for the write command.
    Type: Application
    Filed: August 9, 2019
    Publication date: November 28, 2019
    Inventor: Daniel B. Penney
  • DFE conditioning for write operations of a memory device
    Patent number: 10490241
    Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Liang Chen, David R. Brown
  • ANALOG MULTIPLEXING SCHEME FOR DECISION FEEDBACK EQUALIZERS
    Publication number: 20190356517
    Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Inventors: Raghukiran Sreeramaneni, Daniel B. Penney
  • Signal training for prevention of metastability due to clocking indeterminacy
    Patent number: 10482936
    Abstract: Methods and systems that may employ adjustments to the latencies in the input circuitry to reduce the latency during initialization period and to prevent undesired effects from metastability are provided. Disclosed systems may employ adjustable delays during a signal training process to cause adjustments in the timing of the host that will reduce latencies during write cycles. Certain systems may further reduce latencies by employing input logic circuitry that produces a valid, consistent signal from the bidirectional connection, such as a gate, and preventing metastability in input circuitry altogether. Such circuitry allows bypassing of initialization periods to stabilize the input, and allows further reduction of the initialization.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Management of strobe/clock phase tolerances during extended write preambles
    Patent number: 10482946
    Abstract: Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • APPARATUSES AND METHODS FOR STORING A DATA VALUE IN A SENSING CIRCUITRY ELEMENT
    Publication number: 20190341084
    Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Inventors: Daniel B. Penney, Harish N. Venkata, Guy S. Perry
  • MULTI-PHASE CLOCK DIVISION
    Publication number: 20190325937
    Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.
    Type: Application
    Filed: June 28, 2019
    Publication date: October 24, 2019
    Inventor: Daniel B. Penney
  • Write leveling a memory device
    Patent number: 10452319
    Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Liang Chen
  • MANAGEMENT OF STROBE/CLOCK PHASE TOLERANCES DURING EXTENDED WRITE PREAMBLES
    Publication number: 20190311762
    Abstract: Memory devices coupled to host devices may receive clocking signals and data strobe signals during write operations, which may present a skew. Memory specifications may include Write Preambles, preambles in the data signal provided at the beginning of write operations. Memory devices that decode particular features in the preamble, and that may relax the skew tolerances are provided. The memory devices may include configurable decoders that may be adjusted based on the features in the preamble or the preamble type. For example, memory devices may employ a rising edge, a falling edge, a low level, or a high level based on the specific type of preamble. Skew tolerances between the clock and the data strobe signals may be further improved by employing early write command launch points, using a training mechanism.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 10, 2019
    Inventor: Daniel B. Penney
  • Multi-phase clock division
    Patent number: 10438651
    Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Write level arbiter circuitry
    Patent number: 10431294
    Abstract: Devices and methods include utilizing memory including a group of storage elements, such as memory banks. A command interface is configured to receive a write command to write data to the memory. A data strobe is received to assist in writing the data to the memory. Phase division circuitry is configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory. Arbiter circuitry is configured to detect which phase of the plurality of phases captures a write start signal for the write command.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Column repair in memory
    Patent number: 10418123
    Abstract: Apparatuses and methods related to column repair in memory are described. The sensing circuitry of an apparatus can include a first sensing component, a second sensing component, and a third sensing component. The second sensing component can include a defective sense amplifier that is column repaired. The apparatus can include a controller configured to use the sensing circuitry to shift data from the first sensing component to the third sensing component by transferring the data through the second sensing component. The second sensing component can be physically located between the first sensing component and the third sensing component.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Guy S. Perry, Harish N. Venkata, Glen E. Hush
  • Write signal launch circuitry for memory drive
    Patent number: 10418090
    Abstract: Systems and methods include capture circuitry configured to capture a write signal from a host device using a data strobe signal from the host device and to output one or more indications of capture of the write signal. Calculation circuitry is configured to receive the data strobe signal, receive the one or more indications of capture, and determine a delay between a first edge of the data strobe signal and receipt of the one or more indications of capture. The systems and methods also include transmission and control circuitry configured to launch subsequent write signals at a time based at least in part on the delay.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ming-Bo Liu, Daniel B. Penney
  • SIGNAL TRAINING FOR PREVENTION OF METASTABILITY DUE TO CLOCKING INDETERMINACY
    Publication number: 20190279694
    Abstract: Methods and systems that may employ adjustments to the latencies in the input circuitry to reduce the latency during initialization period and to prevent undesired effects from metastability are provided. Disclosed systems may employ adjustable delays during a signal training process to cause adjustments in the timing of the host that will reduce latencies during write cycles. Certain systems may further reduce latencies by employing input logic circuitry that produces a valid, consistent signal from the bidirectional connection, such as a gate, and preventing metastability in input circuitry altogether. Such circuitry allows bypassing of initialization periods to stabilize the input, and allows further reduction of the initialization.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 12, 2019
    Inventor: Daniel B. Penney
  • Analog multiplexing scheme for decision feedback equalizers
    Patent number: 10411919
    Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals based. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, Daniel B. Penney
  • DFE CONDITIONING FOR WRITE OPERATIONS OF A MEMORY DEVICE
    Publication number: 20190259431
    Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.
    Type: Application
    Filed: July 31, 2018
    Publication date: August 22, 2019
    Inventors: Daniel B. Penney, Liang Chen, David R. Brown
  • GAP DETECTION FOR CONSECUTIVE WRITE OPERATIONS OF A MEMORY DEVICE
    Publication number: 20190259433
    Abstract: Method and devices include a shifter that is configured to receive a write command for a memory device and is configured to produce multiple shifted write commands from the write command. Multiple flip-flops that are configured to receive a subset of the multiple shifted write commands from the shifter. The multiple flip-flops also are configured to output an indicator of whether subsequent write commands of the subset of write commands is asserted when the write command has completed shifting through the shifter as a write start signal.
    Type: Application
    Filed: July 31, 2018
    Publication date: August 22, 2019
    Inventors: Daniel B. Penney, Liang Chen, David R. Brown
  • WRITE LEVEL ARBITER CIRCUITRY
    Publication number: 20190259446
    Abstract: Devices and methods include utilizing memory including a group of storage elements, such as memory banks. A command interface is configured to receive a write command to write data to the memory. A data strobe is received to assist in writing the data to the memory. Phase division circuitry is configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory. Arbiter circuitry is configured to detect which phase of the plurality of phases captures a write start signal for the write command.
    Type: Application
    Filed: July 31, 2018
    Publication date: August 22, 2019
    Inventor: Daniel B. Penney
  • Bank to bank data transfer
    Patent number: 10387046
    Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Thanh K. Mai, Gary L. Howe, Daniel B. Penney