Patents by Inventor Daniel Benoit

Daniel Benoit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10892292
    Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: January 12, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
  • Publication number: 20200381617
    Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.
    Type: Application
    Filed: May 20, 2020
    Publication date: December 3, 2020
    Inventors: Philippe BOIVIN, Daniel BENOIT, Remy BERTHELON
  • Patent number: 10783289
    Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 22, 2020
    Assignee: AUTODESK, INC.
    Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Samuel Eli Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
  • Patent number: 10662173
    Abstract: Compounds of formula (I): wherein Ra, Rb, Rc, Rd, R3, R4, R5, A1, A2, T and W are as defined in the description. Medicinal products containing the same which are useful in treating conditions requiring a pro-apoptotic agent.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: May 26, 2020
    Assignees: LES LABORATOIRES SERVIER, VERNALIS (R&D) LTD
    Inventors: Patrick Casara, Thierry Le Diguarher, Jean-Michel Henlin, Jérôme-Benoît Starck, Arnaud Le Tiran, Guillaume De Nanteuil, Olivier Geneste, James Edward Paul Davidson, James Brooke Murray, I-Jen Chen, Claire Walmsley, Christopher John Graham, Stuart Ray, Daniel Maddox, Simon Bedford
  • Patent number: 10466131
    Abstract: The present relates to a system and a bidirectional differential pressure sensor. The system and bidirectional differential pressure sensor comprise a first adaptor comprising an end configured to receive a first pipe, and a second adaptor comprising an end configured to receive a second pipe. The system and bidirectional differential pressure sensor further comprise a pressure sensing element determining a pressure differential between fluid received via the first adaptor with respect to fluid received via the second adaptor. The system or bidirectional differential pressure sensor further comprise a processing unit executing an algorithm for generating an adjusted pressure differential based on the pressure differential determined by the pressure sensing element.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: November 5, 2019
    Assignee: DISTECH CONTROLS INC.
    Inventors: Daniel Beaudoin, Dominic Gagnon, Pascal Gratton, Simon Benoit
  • Publication number: 20190244989
    Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel BENOIT, Olivier HINSINGER, Emmanuel GOURVEST
  • Publication number: 20190228114
    Abstract: Embodiments disclosed herein provide systems and methods for preparing geometry for 3D printing. In one embodiment, a 3D printing preparation application receives 3D geometry and repairs non-manifold edges and non-manifold vertices, producing a topological manifold geometry. The 3D printing preparation application then welds coincident edges without coincident faces and fills holes in the geometry. The 3D printing preparation application may further perform resolution-aware thickening of the geometry by estimating distances to a medial axis based on distances to distance field shocks, and advecting the distance field using a velocity field. A similar approach may be used to perform resolution-aware separation enforcement. Alternatively, one component may be globally thickened and subtracted from another for separation enforcement. The 3D printing preparation application may also split large models and add connectors for connecting the split pieces after printing.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Saul GRIFFITH, Martin WICKE, Keith PASKO, Geoffrey IRVING, Sam CALISCH, Tucker GILMAN, Daniel BENOIT, Jonathan BACHRACH
  • Patent number: 10304893
    Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
  • Patent number: 10248740
    Abstract: Embodiments disclosed herein provide systems and methods for preparing geometry for 3D printing. In one embodiment, a 3D printing preparation application receives 3D geometry and repairs non-manifold edges and non-manifold vertices, producing a topological manifold geometry. The 3D printing preparation application then welds coincident edges without coincident faces and fills holes in the geometry. The 3D printing preparation application may further perform resolution-aware thickening of the geometry by estimating distances to a medial axis based on distances to distance field shocks, and advecting the distance field using a velocity field. A similar approach may be used to perform resolution-aware separation enforcement. Alternatively, one component may be globally thickened and subtracted from another for separation enforcement. The 3D printing preparation application may also split large models and add connectors for connecting the split pieces after printing.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: April 2, 2019
    Assignee: AUTODESK, INC.
    Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Sam Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
  • Publication number: 20180102385
    Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.
    Type: Application
    Filed: May 11, 2017
    Publication date: April 12, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
  • Publication number: 20180004871
    Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Inventors: Saul GRIFFITH, Martin WICKE, Keith PASKO, Geoffrey IRVING, Samuel Eli CALISCH, Tucker GILMAN, Daniel BENOIT, Jonathan BACHRACH
  • Patent number: 9767233
    Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: September 19, 2017
    Assignee: AUTODESK, INC.
    Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Samuel Eli Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
  • Patent number: 9666679
    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: May 30, 2017
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Clement Gaumer, Daniel Benoit
  • Patent number: 9619587
    Abstract: Embodiments disclosed herein provide techniques for decomposing 3D geometry into developable surface patches and cut patterns. In one embodiment, a decomposition application receives a triangulated 3D surface as input and determines approximately developable surface patches from the 3D surface using a variant of k-means clustering. Such approximately developable surface patches may have undesirable jagged boundaries, which the decomposition application may eliminate by generating a data structure separate from the mesh that contains patch boundaries and optimizing the patch boundaries or, alternatively, remeshing the mesh such that patch boundaries fall on mesh edges. The decomposition application may then flatten the patches into truly developable surfaces by re-triangulating the patches as ruled surfaces. The decomposition application may further flatten the ruled surfaces into 2D shapes and lay those shapes out on virtual sheets of material.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: April 11, 2017
    Assignee: AUTODESK, INC.
    Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Sam Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
  • Publication number: 20170061051
    Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.
    Type: Application
    Filed: November 14, 2016
    Publication date: March 2, 2017
    Inventors: Saul GRIFFITH, Martin WICKE, Keith PASKO, Geoffrey IRVING, Samuel Eli CALISCH, Tucker GILMAN, Daniel BENOIT, Jonathan BACHRACH
  • Publication number: 20160343814
    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
    Type: Application
    Filed: August 3, 2016
    Publication date: November 24, 2016
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Clement Gaumer, Daniel Benoit
  • Patent number: 9495484
    Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: November 15, 2016
    Assignee: AUTODESK, LLP
    Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Samuel Eli Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
  • Patent number: 9437694
    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 6, 2016
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Clement Gaumer, Daniel Benoit
  • Patent number: 8765575
    Abstract: A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO2 layer and penetrating into a silicon support, this method including the steps of forming on the silicon layer a second SiO2 layer and a first silicon nitride layer, forming the trench, and performing a first oxidizing processing to form a third SiO2 layer; performing a second oxidizing processing to form, on the exposed surfaces of the first silicon nitride layer a fourth SiO2 layer; depositing a second silicon nitride layer and filling the trench with SiO2; and removing the upper portion of the structure until the upper surface of the silicon layer is exposed.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel Benoit, Laurent Favennec
  • Publication number: 20140081603
    Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 20, 2014
    Applicant: AUTODESK, Inc.
    Inventors: Saul GRIFFITH, Martin WICKE, Keith PASKO, Geoffrey IRVING, Samuel Eli CALISCH, Tucker GILMAN, Daniel BENOIT, Jonathan BACHRACH