Patents by Inventor Daniel Benoit
Daniel Benoit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260144041Abstract: The present description concerns a manufacturing method. A first dielectric layer, a first oxide layer, a second dielectric layer, and a second oxide layer are successively deposited on a first metal level. An anneal is performed before depositing a third dielectric layer. A via and a line metallization of a second metal level are then formed through the dielectric and oxide layers, all the way to the first metal level.Type: ApplicationFiled: September 29, 2025Publication date: May 21, 2026Applicant: STMicroelectronics International N.V.Inventors: Jean-Christophe GIRAUDIN, Daniel BENOIT, Rossella RANICA
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Publication number: 20250143193Abstract: The present description relates to a method of manufacturing an electronic device comprising a phase-change memory cell, the method comprising: the forming of a first layer made of a resistive material; the forming of a stack of layers on the first layer, the stack comprising at least one second layer made of a phase-change material; the etching of the stack, said etching stopping when the first layer is reached around the location of the memory cell; the forming of a spacer on the side walls of the stack; then an etching of the first layer, so that the stack rests on a central portion of the first layer and that the spacer rests on a peripheral portion of the first layer.Type: ApplicationFiled: October 22, 2024Publication date: May 1, 2025Applicants: STMicroelectronics International N.V., COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Latifa DESVOIVRES, Jerome DUBOIS, Daniel BENOIT, Pascal GOURAUD
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Publication number: 20240334712Abstract: A memory cell comprising a stack of a conductive via, of a layer made of a phase-change material, and of a first electrode, the memory cell being covered with an encapsulation layer made of a silicon nitride having a density or volumic mass smaller than 2.2 g/cm3. A method of manufacturing a memory cell and a system having an integrated memory circuit that includes a plurality of memory cells is also provided.Type: ApplicationFiled: March 26, 2024Publication date: October 3, 2024Applicant: STMicroelectronics International N.V.Inventor: Daniel BENOIT
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Patent number: 11800821Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.Type: GrantFiled: July 1, 2022Date of Patent: October 24, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Daniel Benoit, Remy Berthelon
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Publication number: 20220336736Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Applicants: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe BOIVIN, Daniel BENOIT, Remy BERTHELON
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Patent number: 11411177Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.Type: GrantFiled: May 20, 2020Date of Patent: August 9, 2022Assignees: STMicroelectronics (Crolles 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Philippe Boivin, Daniel Benoit, Remy Berthelon
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Patent number: 11203157Abstract: Embodiments disclosed herein provide systems and methods for preparing geometry for 3D printing. In one embodiment, a 3D printing preparation application receives 3D geometry and repairs non-manifold edges and non-manifold vertices, producing a topological manifold geometry. The 3D printing preparation application then welds coincident edges without coincident faces and fills holes in the geometry. The 3D printing preparation application may further perform resolution-aware thickening of the geometry by estimating distances to a medial axis based on distances to distance field shocks, and advecting the distance field using a velocity field. A similar approach may be used to perform resolution-aware separation enforcement. Alternatively, one component may be globally thickened and subtracted from another for separation enforcement. The 3D printing preparation application may also split large models and add connectors for connecting the split pieces after printing.Type: GrantFiled: April 2, 2019Date of Patent: December 21, 2021Assignee: AUTODESK, INC.Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Sam Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
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Patent number: 10892292Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.Type: GrantFiled: April 17, 2019Date of Patent: January 12, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
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Publication number: 20200381617Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.Type: ApplicationFiled: May 20, 2020Publication date: December 3, 2020Inventors: Philippe BOIVIN, Daniel BENOIT, Remy BERTHELON
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Patent number: 10783289Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.Type: GrantFiled: September 15, 2017Date of Patent: September 22, 2020Assignee: AUTODESK, INC.Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Samuel Eli Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
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Publication number: 20190244989Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Daniel BENOIT, Olivier HINSINGER, Emmanuel GOURVEST
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Publication number: 20190228114Abstract: Embodiments disclosed herein provide systems and methods for preparing geometry for 3D printing. In one embodiment, a 3D printing preparation application receives 3D geometry and repairs non-manifold edges and non-manifold vertices, producing a topological manifold geometry. The 3D printing preparation application then welds coincident edges without coincident faces and fills holes in the geometry. The 3D printing preparation application may further perform resolution-aware thickening of the geometry by estimating distances to a medial axis based on distances to distance field shocks, and advecting the distance field using a velocity field. A similar approach may be used to perform resolution-aware separation enforcement. Alternatively, one component may be globally thickened and subtracted from another for separation enforcement. The 3D printing preparation application may also split large models and add connectors for connecting the split pieces after printing.Type: ApplicationFiled: April 2, 2019Publication date: July 25, 2019Inventors: Saul GRIFFITH, Martin WICKE, Keith PASKO, Geoffrey IRVING, Sam CALISCH, Tucker GILMAN, Daniel BENOIT, Jonathan BACHRACH
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Patent number: 10304893Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.Type: GrantFiled: May 11, 2017Date of Patent: May 28, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
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Patent number: 10248740Abstract: Embodiments disclosed herein provide systems and methods for preparing geometry for 3D printing. In one embodiment, a 3D printing preparation application receives 3D geometry and repairs non-manifold edges and non-manifold vertices, producing a topological manifold geometry. The 3D printing preparation application then welds coincident edges without coincident faces and fills holes in the geometry. The 3D printing preparation application may further perform resolution-aware thickening of the geometry by estimating distances to a medial axis based on distances to distance field shocks, and advecting the distance field using a velocity field. A similar approach may be used to perform resolution-aware separation enforcement. Alternatively, one component may be globally thickened and subtracted from another for separation enforcement. The 3D printing preparation application may also split large models and add connectors for connecting the split pieces after printing.Type: GrantFiled: April 9, 2013Date of Patent: April 2, 2019Assignee: AUTODESK, INC.Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Sam Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
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Publication number: 20180102385Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.Type: ApplicationFiled: May 11, 2017Publication date: April 12, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Daniel Benoit, Olivier Hinsinger, Emmanuel Gourvest
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Publication number: 20180004871Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.Type: ApplicationFiled: September 15, 2017Publication date: January 4, 2018Inventors: Saul GRIFFITH, Martin WICKE, Keith PASKO, Geoffrey IRVING, Samuel Eli CALISCH, Tucker GILMAN, Daniel BENOIT, Jonathan BACHRACH
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Patent number: 9767233Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.Type: GrantFiled: November 14, 2016Date of Patent: September 19, 2017Assignee: AUTODESK, INC.Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Samuel Eli Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
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Patent number: 9666679Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.Type: GrantFiled: August 3, 2016Date of Patent: May 30, 2017Assignee: STMicroelectronics (Crolles 2) SASInventors: Clement Gaumer, Daniel Benoit
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Patent number: 9619587Abstract: Embodiments disclosed herein provide techniques for decomposing 3D geometry into developable surface patches and cut patterns. In one embodiment, a decomposition application receives a triangulated 3D surface as input and determines approximately developable surface patches from the 3D surface using a variant of k-means clustering. Such approximately developable surface patches may have undesirable jagged boundaries, which the decomposition application may eliminate by generating a data structure separate from the mesh that contains patch boundaries and optimizing the patch boundaries or, alternatively, remeshing the mesh such that patch boundaries fall on mesh edges. The decomposition application may then flatten the patches into truly developable surfaces by re-triangulating the patches as ruled surfaces. The decomposition application may further flatten the ruled surfaces into 2D shapes and lay those shapes out on virtual sheets of material.Type: GrantFiled: April 9, 2013Date of Patent: April 11, 2017Assignee: AUTODESK, INC.Inventors: Saul Griffith, Martin Wicke, Keith Pasko, Geoffrey Irving, Sam Calisch, Tucker Gilman, Daniel Benoit, Jonathan Bachrach
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Publication number: 20170061051Abstract: Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.Type: ApplicationFiled: November 14, 2016Publication date: March 2, 2017Inventors: Saul GRIFFITH, Martin WICKE, Keith PASKO, Geoffrey IRVING, Samuel Eli CALISCH, Tucker GILMAN, Daniel BENOIT, Jonathan BACHRACH