Patents by Inventor Daniel C. Edelstein

Daniel C. Edelstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220115269
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha
  • Patent number: 11232983
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: January 25, 2022
    Assignee: Tessera, Inc.
    Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 11222817
    Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: January 11, 2022
    Assignee: Tessera, Inc.
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 11217742
    Abstract: A structure and a method for fabricating a bottom electrode for an integrated circuit device are described. A first dielectric layer is provided over a substrate and the first dielectric layer has a recess. A bottom electrode is formed over the recess. The bottom electrode consists of a microstud layer disposed completely within the recess of the dielectric and conforming to the recess, a bottom pedestal disposed on a top surface of the microstud and a top pedestal on a top surface of the bottom pedestal. The material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud. A conductive element of the integrated circuit device is formed on a top surface of the bottom electrode. A first portion of the bottom electrode is disposed in and conforms to the recess. A second portion of the bottom electrode and the conductive element are conical sections.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theodorus E Standaert, Daniel C Edelstein
  • Patent number: 11145813
    Abstract: A conductive microstud is formed in a recess of an insulator layer formed on the substrate. A bottom pedestal is formed on a top surface of the microstud. The material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud. A top pedestal is formed on a top surface of the bottom pedestal. The top surface of at least one of the bottom pedestal and top pedestal is planarized. A conductive layer is formed on a top surface of the top pedestal. Next, a conical structure is formed. The conical structure is comprised of at least the conductive layer and a top portion of the top pedestal.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Theodorus E Standaert, Daniel C Edelstein
  • Patent number: 11081643
    Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel C. Edelstein
  • Publication number: 20210226120
    Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Inventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel C. Edelstein
  • Patent number: 11056425
    Abstract: A structure comprising a first dielectric layer embedded with a first interconnect structure. An insulator layer is disposed on the first dielectric layer. A second dielectric layer is disposed on the insulator layer. A via resides within the second dielectric layer. A second interconnect structure is isolated from the first dielectric layer. A first portion of a bottom surface of the via resides on a top surface of the insulator layer. A second portion of the bottom surface of the via resides on a first portion of a top surface of the first interconnect structure.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Publication number: 20200402848
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 10833258
    Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein, Karthik Yogendra, John C. Arnold
  • Publication number: 20200350495
    Abstract: MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.
    Type: Application
    Filed: May 2, 2019
    Publication date: November 5, 2020
    Inventors: Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein, Karthik Yogendra, John C. Arnold
  • Patent number: 10777735
    Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Daniel C. Edelstein, Bruce B. Doris, Henry K. Utomo, Theodorus E. Standaert, Nathan P. Marchack
  • Patent number: 10770347
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 8, 2020
    Assignee: Tessera, Inc.
    Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
  • Publication number: 20200227317
    Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Applicant: Tessera, Inc.
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 10714683
    Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, Isabel C. Chu, John C. Arnold
  • Patent number: 10686124
    Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Daniel C. Edelstein, Bruce B. Doris, Henry K. Utomo, Theodorus E. Standaert, Nathan P. Marchack
  • Patent number: 10680169
    Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, Isabel C. Chu, John C. Arnold
  • Publication number: 20200144491
    Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.
    Type: Application
    Filed: December 18, 2019
    Publication date: May 7, 2020
    Inventors: Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, Isabel C. Chu, John C. Arnold
  • Publication number: 20200144498
    Abstract: A conductive microstud is formed in a recess of an insulator layer formed on the substrate. A bottom pedestal is formed on a top surface of the microstud. The material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud. A top pedestal is formed on a top surface of the bottom pedestal. The top surface of at least one of the bottom pedestal and top pedestal is planarized. A conductive layer is formed on a top surface of the top pedestal. Next, a conical structure is formed. The conical structure is comprised of at least the conductive layer and a top portion of the top pedestal.
    Type: Application
    Filed: January 3, 2020
    Publication date: May 7, 2020
    Inventors: Chih-Chao Yang, Theodorus E. Standaert, Daniel C. Edelstein
  • Patent number: 10615074
    Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 7, 2020
    Assignee: Tessera, Inc.
    Inventors: Daniel C. Edelstein, Chih-Chao Yang