Abstract: A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.

Abstract: An integrated circuit, including a substrate, at least one metal wiring layer disposed above the substrate. The metal wiring layer including a wiring switch and a plurality of patterned conductors. The wiring switch including a back gate field effect transistor (BGFET).

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Abstract: Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

Abstract: An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

Abstract: An interconnect structure and method for forming a multi-layered seed layer for semiconductor interconnections are disclosed. Specifically, the method and structure involves utilizing sequential catalytic chemical vapor deposition, which is followed by annealing, to form the multi-layered seed layer of an interconnect structure. The multi-layered seed layer will improve electromigration resistance, decrease void formation, and enhance reliability of ultra-large-scale integration (ULSI) chips.

Abstract: A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

Abstract: An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be lithographically patterned and cut along a line at an angle less than 45 degrees from the lengthwise direction of the plurality of conductive lines. Alternately, a copolymer mixed with homopolymer may be placed into a recessed area and self-aligned to form a plurality of conductive lines having a sublithographic pitch in the constant width region and a lithographic dimension between adjacent lines at a trapezoidal region. Yet alternately, a first plurality of conductive lines with the sublithographic pitch and a second plurality of conductive lines with the lithographic pitch may be formed at the same level or at different.

Abstract: An interconnect structure is provided that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing. The metal interconnect is formed in a dielectric material. A metal cap is selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.

Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.

Abstract: A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Abstract: A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

Abstract: An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.

Abstract: A method of forming a barrier layer for metal interconnects of an integrated circuit device includes forming a first cap layer over a top surface of a conductive line of the integrated circuit device in a manner that facilitates a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line.

Abstract: An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.

Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.