Patents by Inventor Daniel C. Worledge

Daniel C. Worledge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7907440
    Abstract: A method is provided for writing data to an MRAM device having a plurality of magnetic memory cells configured in an array between a plurality of word lines and bit lines. At least one of the magnetic memory cells includes at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one first parallel coupling layer, and a third free magnetic layer separated from the second free magnetic layer by at least one second parallel coupling layer. A magnetic moment of the second free magnetic layer is greater than both a magnetic moment of the first free magnetic layer and the third free magnetic layer.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: March 15, 2011
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7893470
    Abstract: Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer being configured to provide ferromagnetic exchange coupling between the layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. The semiconductor device may comprise magnetic random access memory (MRAM). In another aspect, a method for coupling magnetic layers in a semiconductor device comprising at least two magnetic layers and a spacer layer therebetween, the method comprises the following step.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7894247
    Abstract: A magnetic memory cell is provided. The magnetic memory cell includes at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one spacer layer, and a third free magnetic layer separated from the second free magnetic layer by at least one anti-parallel coupling layer. A magnetic moment of the first free magnetic layer is greater than both a magnetic moment of the second free magnetic layer and a magnetic moment of the third free magnetic layer. The magnetic memory cell may be used in conjunction with a magnetic random access memory device.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7880250
    Abstract: A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least partially, between the source electrode and the drain electrode. The magnetoelectric region of the insulating material, when energized, is configured to change magnetic state of the insulating material. The gate electrode is positioned proximate the magnetoelectric region of the insulating material.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Publication number: 20100264475
    Abstract: A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least partially, between the source electrode and the drain electrode. The magnetoelectric region of the insulating material, when energized, is configured to change magnetic state of the insulating material. The gate electrode is positioned proximate the magnetoelectric region of the insulating material.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 21, 2010
    Applicant: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Publication number: 20100258849
    Abstract: A magnetic tunnel junction transistor. In a particular embodiment, the magnetic tunnel junction transistor includes a tunnel barrier having a high resistance when in a non-ferromagnetic state, and a low resistance when in a ferromagnetic state. The tunnel barrier is switchable between the non-ferromagnetic and the ferromagnetic states.
    Type: Application
    Filed: June 26, 2010
    Publication date: October 14, 2010
    Applicant: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7791152
    Abstract: A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least partially, between the source electrode and the drain electrode. The magnetoelectric region of the insulating material, when energized, is configured to change magnetic state of the insulating material. The gate electrode is positioned proximate the magnetoelectric region of the insulating material.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Publication number: 20090298202
    Abstract: Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer being configured to provide ferromagnetic exchange coupling between the layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. The semiconductor device may comprise magnetic random access memory (MRAM). In another aspect, a method for coupling magnetic layers in a semiconductor device comprising at least two magnetic layers and a spacer layer therebetween, the method comprises the following step.
    Type: Application
    Filed: August 11, 2009
    Publication date: December 3, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Daniel C. Worledge
  • Publication number: 20090279353
    Abstract: A magnetic tunnel junction transistor and method of operating the same. In a particular embodiment, the magnetic tunnel junction transistor includes electrically conductive source, drain and gate electrodes. An electrically insulating material having a non-magnetoelectric region and a magnetoelectric region is positioned such that the non-magnetoelectric region is, at least partially, between the source electrode and the drain electrode. The magnetoelectric region of the insulating material, when energized, is configured to change magnetic state of the insulating material. The gate electrode is positioned proximate the magnetoelectric region of the insulating material.
    Type: Application
    Filed: May 12, 2008
    Publication date: November 12, 2009
    Inventor: Daniel C. Worledge
  • Publication number: 20090235018
    Abstract: Magnetic random access memory (MRAM) devices and techniques for use thereof are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer; at least one first free magnetic layer separated from the fixed magnetic layer by at least one barrier layer; at least one second free magnetic layer separated from the first free magnetic layer by at least one spacer layer; and at least one capping layer over a side of the second free magnetic layer opposite the spacer layer. One or more of the first free magnetic layer and the second free magnetic layer comprise at least one rare earth element, such that the at least one rare earth element makes up between about one percent and about 10 percent of one or more of the first free magnetic layer and the second free magnetic layer.
    Type: Application
    Filed: March 12, 2008
    Publication date: September 17, 2009
    Applicant: International Business Machine Corporation
    Inventors: William J. Gallagher, Daniel C. Worledge
  • Publication number: 20080259675
    Abstract: A method is provided for writing data to an MRAM device having a plurality of magnetic memory cells configured in an array between a plurality of word lines and bit lines. At least one of the magnetic memory cells includes at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one first parallel coupling layer, and a third free magnetic layer separated from the second free magnetic layer by at least one second parallel coupling layer. A magnetic moment of the second free magnetic layer is greater than both a magnetic moment of the first free magnetic layer and the third free magnetic layer.
    Type: Application
    Filed: May 12, 2008
    Publication date: October 23, 2008
    Applicant: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Publication number: 20080259674
    Abstract: A magnetic memory cell is provided. The magnetic memory cell includes at least one fixed magnetic layer, and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one first parallel coupling layer, and a third free magnetic layer separated from the second free magnetic layer by at least one second parallel coupling layer. A magnetic moment of the second free magnetic layer is greater than both a magnetic moment of the first free magnetic layer and a magnetic moment of the third free magnetic layer. The magnetic memory cell may be used in conjunction with a magnetic random access memory device.
    Type: Application
    Filed: May 12, 2008
    Publication date: October 23, 2008
    Applicant: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7433225
    Abstract: A method is provided for writing data to an MRAM device having a plurality of magnetic memory cells configured in an array between a plurality of word lines and bit lines. At least one of the magnetic memory cells includes at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one spacer layer, and a third free magnetic layer separated from the second free magnetic layer by at least one anti-parallel coupling layer. A magnetic moment of the first free magnetic is greater than both a magnetic moment of the second free magnetic layer and a magnetic moment of the third free magnetic layer.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: October 7, 2008
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Publication number: 20080212365
    Abstract: A magnetic memory cell is provided. The magnetic memory cell includes at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one spacer layer, and a third free magnetic layer separated from the second free magnetic layer by at least one anti-parallel coupling layer. A magnetic moment of the first free magnetic layer is greater than both a magnetic moment of the second free magnetic layer and a magnetic moment of the third free magnetic layer. The magnetic memory cell may be used in conjunction with a magnetic random access memory device.
    Type: Application
    Filed: May 12, 2008
    Publication date: September 4, 2008
    Applicant: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Publication number: 20080007990
    Abstract: Techniques for data storage are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer and a plurality of free magnetic layers, separated from the at least one fixed magnetic layer by at least one barrier layer. The free magnetic layers include a first free magnetic layer adjacent to the barrier layer, a second free magnetic layer separated from the first free magnetic layer by at least one spacer layer, and a third free magnetic layer separated from the second free magnetic layer by at least one anti-parallel coupling layer. A magnetic moment of the first free magnetic layer is greater than both a magnetic moment of the second free magnetic layer and a magnetic moment of the third free magnetic layer.
    Type: Application
    Filed: July 6, 2006
    Publication date: January 10, 2008
    Applicant: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7274057
    Abstract: Techniques for reducing switching fields in semiconductor devices are provided. In one aspect, a semiconductor device comprising at least a first magnetic layer and a second magnetic layer with a spacer layer therebetween is provided. The semiconductor device is configured such that a thickness of at least one of the first magnetic layer and the second magnetic layer maintains a desired activation energy of the semiconductor device in the presence of an applied offsetting magnetic field. A method of reducing a switching field of a semiconductor device having at least a first magnetic layer and a second magnetic layer with a spacer layer therebetween is also provided.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: September 25, 2007
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7045838
    Abstract: Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer being configured to provide ferromagnetic exchange coupling between the layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. The semiconductor device may comprise magnetic random access memory (MRAM). In another aspect, a method for coupling magnetic layers in a semiconductor device comprising at least two magnetic layers and a spacer layer therebetween, the method comprises the following step.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: May 16, 2006
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Publication number: 20020064004
    Abstract: A dual spin filter tunnel junction and a method of operating the junction to control the tunneling of charge carriers. The tunnel junction has a polarization-selective barrier profile for charge carriers and is made of a first spin filter and a second spin filter adjacent the first spin filter. The first spin filter has a first magnetization M1 and the second spin filter has a second magnetization M2 and the relation between magnetizations M1, M2 such as their relative alignment is alterable, e.g., by applying an external magnetic field to change the orientation of either M1 or M2 or both, thereby changing the polarization-selective barrier profile to control the tunneling of the charge carriers. The dual spin filter tunnel junction has an excellent ratio of high to low resistance Rhi/Rlow and can be used in sensors, nonvolatile memories and other devices relying on magnetically induced resistance changes.
    Type: Application
    Filed: August 7, 2001
    Publication date: May 30, 2002
    Inventor: Daniel C. Worledge