Patents by Inventor Daniel Charles Edelstein
Daniel Charles Edelstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11031542Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.Type: GrantFiled: May 2, 2019Date of Patent: June 8, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Daniel Charles Edelstein, Michael Rizzolo, Theodorus E. Standaert
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Publication number: 20210134883Abstract: A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.Type: ApplicationFiled: November 4, 2019Publication date: May 6, 2021Inventors: Ashim DUTTA, Chih-Chao YANG, Daniel Charles EDELSTEIN, John ARNOLD, Theodorus E. STANDAERT
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Publication number: 20210104406Abstract: An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Inventors: Chih-Chao Yang, Daniel Charles Edelstein, Chao-Kun Hu, Oscar Van der Straten
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Publication number: 20210013400Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.Type: ApplicationFiled: July 9, 2019Publication date: January 14, 2021Inventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel Charles Edelstein
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Patent number: 10892404Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.Type: GrantFiled: July 9, 2019Date of Patent: January 12, 2021Assignee: International Business Machines CorporationInventors: Ashim Dutta, Saba Zare, Michael Rizzolo, Theodorus E. Standaert, Daniel Charles Edelstein
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Publication number: 20200350486Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.Type: ApplicationFiled: May 2, 2019Publication date: November 5, 2020Inventors: Chih-Chao Yang, Daniel Charles Edelstein, Michael Rizzolo, Theodorus E. Standaert
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Patent number: 9824917Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.Type: GrantFiled: April 25, 2017Date of Patent: November 21, 2017Assignee: International Business Machines CorporationInventors: Chih-chao Yang, Daniel Charles Edelstein
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Publication number: 20170301620Abstract: The disclosure relates to semiconductor interconnect structure having enhanced electromigration (EM) reliability in which an oxygen scavenger layer deposited (directly or indirectly) over a surface of conductive material.Type: ApplicationFiled: April 15, 2016Publication date: October 19, 2017Inventors: Chih-chao YANG, Daniel Charles EDELSTEIN
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Publication number: 20170301584Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.Type: ApplicationFiled: April 25, 2017Publication date: October 19, 2017Inventors: Chih-chao YANG, Daniel Charles EDELSTEIN
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Patent number: 9702042Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.Type: GrantFiled: November 16, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Chih-chao Yang, Daniel Charles Edelstein
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Patent number: 9536780Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.Type: GrantFiled: April 15, 2016Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Chih-chao Yang, Daniel Charles Edelstein
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Publication number: 20100252775Abstract: An indium cap layer is formed by blanket depositing indium onto a surface of metallic interconnects separated by interlayer dielectric, and then selectively chemically etching the indium located on the interlayer dielectric leaving an indium cap layer. Etchants containing a strong acid are provided for selectively removing the indium.Type: ApplicationFiled: June 21, 2010Publication date: October 7, 2010Applicant: International Business Machines CorporationInventors: Maurice McGlashan-Powell, Eugene J. O'Sullivan, Daniel Charles Edelstein
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Publication number: 20080179280Abstract: An indium cap layer is formed by blanket depositing indium onto a surface of metallic interconnects separated by interlayer dielectric, and then selectively chemically etching the indium located on the interlayer dielectric leaving an indium cap layer. Etchants containing a strong acid are provided for selectively removing the indium.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Applicant: International Business Machines CorporationInventors: Maurice McGlashan-Powell, Eugene J. O'Sullivan, Daniel Charles Edelstein
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Patent number: 7276787Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: GrantFiled: December 5, 2003Date of Patent: October 2, 2007Assignee: International Business Machines CorporationInventors: Daniel Charles Edelstein, Paul Stephen Andry, Leena Paivikki Buchwalter, Jon Alfred Casey, Sherif A. Goma, Raymond R. Horton, Gareth Geoffrey Hougham, Michael Wayne Lane, Xiao Hu Liu, Chirag Suryakant Patel, Edmund Juris Sprogis, Michelle Leigh Steen, Brian Richard Sundlof, Cornelia K. Tsang, George Frederick Walker
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Publication number: 20040229456Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.Type: ApplicationFiled: February 9, 2004Publication date: November 18, 2004Applicant: International Business MachinesInventors: Panayotis Constantinou Andricacos, Hariklia Deligianni, John Owen Dukovic, Daniel Charles Edelstein, Wilma Jean Horkans, Chao-Kun Hu, Jeffrey Louis Hurd, Kenneth Parker Rodbell, Cyprian Emeka Uzoh, Kwong-Hon Wong
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Publication number: 20040195694Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits. good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: ApplicationFiled: April 23, 2004Publication date: October 7, 2004Applicant: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas Mcarraoll Shaw
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Patent number: 6777809Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: GrantFiled: December 19, 2002Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas Mcarraoll Shaw
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Patent number: 6709562Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.Type: GrantFiled: July 6, 1999Date of Patent: March 23, 2004Assignee: International Business Machines CorporationInventors: Panayotis Constantinou Andricacos, Hariklia Deligianni, John Owen Dukovic, Daniel Charles Edelstein, Wilma Jean Horkans, Chao-Kun Hu, Jeffrey Louis Hurd, Kenneth Parker Rodbell, Cyprian Emeka Uzoh, Kwong-Hon Wong
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Patent number: 6646345Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.Type: GrantFiled: September 27, 2001Date of Patent: November 11, 2003Assignee: International Business Machines CorporationInventors: Carlos Juan Sambucetti, Judith Marie Rubino, Daniel Charles Edelstein, Cyryl Cabral, Jr., George Frederick Walker, John G Gaudiello, Horatio Seymour Wildman
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Publication number: 20030089943Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: ApplicationFiled: December 19, 2002Publication date: May 15, 2003Applicant: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas Mcarraoll Shaw