Patents by Inventor Daniel Charles Edelstein
Daniel Charles Edelstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030085447Abstract: An IC including a resistor which is coupled to a metal wiring level through metal contacts, said resistor including a discrete metal-insulator-metal stack, wherein said metal contacts are in contact to one of said metals of said film stack. In the above IC design, current flows laterally through either the top metal electrode, the bottom metal electrode, or both, and any unused electrode is disconnected from the circuit.Type: ApplicationFiled: December 16, 2002Publication date: May 8, 2003Applicant: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas McCarroll Shaw
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Patent number: 6548901Abstract: An interconnect structure having reduced fringing fields of bottom corners of said interconnect structure and a method of fabricating the same is provided. The interconnect structure includes one or more interconnect levels one on top of each other, wherein each interconnect level is separated by a diffusion barrier and includes a dielectric stack of at least one low-k interlayer dielectric on at least one hybrid dielectric, said dielectrics having planar interfaces therebetween, each interconnect level further comprising metallic lines formed in said low-k interlayer dielectric, with the proviso that bottom horizontal portions of said metallic lines are not coincident with said interface, and said metallic lines are contained within said low-k interlayer dielectric. The interconnect structures may be fabricated such that top horizontal portions of the metallic lines are coplanar with a top surface of the low-k interlayer dielectric.Type: GrantFiled: June 15, 2000Date of Patent: April 15, 2003Assignee: International Business Machines CorporationInventors: William Cote, Timothy Joseph Dalton, Daniel Charles Edelstein, Stephen McConnell Gates
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Patent number: 6525427Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: GrantFiled: January 22, 2002Date of Patent: February 25, 2003Assignee: International Business Machines CorporationInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas Mcarraoll Shaw
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Patent number: 6522304Abstract: An integrated horn antenna device with an integrated circuit (IC) chip including a metallic horn structure having a wide aperture, a horizontal waveguide with a tapered via that electromagnetically communicates with a vertical waveguide structure to transmit energy to and from an electronic sub-component transceiver device forming part of the IC chip. Another embodiment of the invention comprises a plurality of multiple discrete IC chips having the integrated horn antenna devices incorporated therewith forming a module for data transmissions between these IC chips. Another embodiment of the invention includes additional external waveguide structures such as optical fibers external to the chips, where radiation is aligned between the horn structures and these waveguides. Dual damascene processing is used to fabricate the horn antenna device within the IC chip.Type: GrantFiled: April 11, 2001Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Arne Watson Ballantine, Daniel Charles Edelstein, James Spiros Nakos, Anthony Kendall Stamper
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Patent number: 6486557Abstract: A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.Type: GrantFiled: February 29, 2000Date of Patent: November 26, 2002Assignee: International Business Machines CorporationInventors: Charles R. Davis, Daniel Charles Edelstein, John C. Hay, Jeffrey C. Hedrick, Christopher Jahnes, Vincent McGahay, Henry A. Nye, III
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Publication number: 20020149530Abstract: An integrated horn antenna device with an integrated circuit (IC) chip including a metallic horn structure having a wide aperture, a horizontal waveguide with a tapered via that electromagnetically communicates with a vertical waveguide structure to transmit energy to and from an electronic sub-component transceiver device forming part of the IC chip. Another embodiment of the invention comprises a plurality of multiple discrete IC chips having the integrated horn antenna devices incorporated therewith forming a module for data transmissions between these IC chips. Another embodiment of the invention includes additional external waveguide structures such as optical fibers external to the chips, where radiation is aligned between the horn structures and these waveguides. Dual damascene processing is used to fabricate the horn antenna device within the IC chip.Type: ApplicationFiled: April 11, 2001Publication date: October 17, 2002Applicant: International Business Machines CorporationInventors: Arne Watson Ballantine, Daniel Charles Edelstein, James Spiros Nakos, Anthony Kendall Stamper
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Publication number: 20020123220Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.Type: ApplicationFiled: September 27, 2001Publication date: September 5, 2002Applicant: International Business Machines CorporationInventors: Carlos Juan Sambucetti, Judith Marie Rubino, Daniel Charles Edelstein, Cyryl Cabral, George Frederick Walker, John G. Gaudiello, Horatio Seymour Wildman
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Patent number: 6437440Abstract: An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.Type: GrantFiled: January 16, 2001Date of Patent: August 20, 2002Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Patrick William Dehaven, Daniel Charles Edelstein, David Peter Klaus, James Manley Pollard, III, Carol L. Stanis, Cyprian Emeka Uzoh
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Publication number: 20020066919Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: ApplicationFiled: January 22, 2002Publication date: June 6, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas McCarraoll Shaw
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Patent number: 6399496Abstract: The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.Type: GrantFiled: November 16, 2000Date of Patent: June 4, 2002Assignee: International Business Machines CorporationInventors: Daniel Charles Edelstein, James McKell Edwin Harper, Chao-Kun Hu, Andrew H. Simon, Cyprian Emeka Uzoh
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Publication number: 20020046874Abstract: An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.Type: ApplicationFiled: January 16, 2001Publication date: April 25, 2002Applicant: International Business Machines CorporationInventors: Cyril Cabral, Patrick William Dehaven, Daniel Charles Edelstein, David Peter Klaus, James Manley Pollard, Carol L. Stanis, Cyprian Emeka Uzoh
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Patent number: 6323128Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.Type: GrantFiled: May 26, 1999Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Carlos Juan Sambucetti, Judith Marie Rubino, Daniel Charles Edelstein, Cyryl Cabral, Jr., George Frederick Walker, John G Gaudiello, Horatio Seymour Wildman
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Publication number: 20010040271Abstract: An IC including a resistor which is coupled to a metal wiring level through metal contacts, said resistor including a discrete metal-insulator-metal stack, wherein said metal contacts are in contact to one of said metals of said film stack. In the above IC design, current flows laterally through either the top metal electrode, the bottom metal electrode, or both, and any unused electrode is disconnected from the circuit.Type: ApplicationFiled: January 9, 2001Publication date: November 15, 2001Inventors: Peter Richard Duncombe, Daniel Charles Edelstein, Robert Benjamin Laibowitz, Deborah Ann Neumayer, Tak Hung Ning, Robert Rosenberg, Thomas McCarroll Shaw
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Patent number: 6301903Abstract: A method and apparatus for activating fusible links on a circuit substrate. The circuit substrate is supported in a fixture which is cooled to a below ambient temperature. Cooling of the circuit substrate decreases the absorption of energy by the substrate, permitting a smaller spot size laser beam having a lower wavelength to be employed for interrupting the fusible links. The substrate is cooled by a refrigeration coil in heat transfer with the fixture holding the substrate. Moisture formation is avoided by placing the substrate and laser source in a controlled atmosphere.Type: GrantFiled: February 2, 2000Date of Patent: October 16, 2001Assignee: International Business Machines CorporationInventors: Daniel Charles Edelstein, Chandrasekhar Narayan
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Patent number: 6291885Abstract: An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.Type: GrantFiled: July 18, 1997Date of Patent: September 18, 2001Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Patrick William DeHaven, Daniel Charles Edelstein, David Peter Klaus, James Manley Pollard, III, Carol L. Stanis, Cyprian Emeka Uzoh
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Publication number: 20010013660Abstract: An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.Type: ApplicationFiled: January 4, 1999Publication date: August 16, 2001Inventors: PETER RICHARD DUNCOMBE, DANIEL CHARLES EDELSTEIN, ROBERT BENJAMIN LAIBOWITZ, DEBORAH ANN NEUMAYER, TAK HUNG NING, ROBERT ROSENBERG, THOMAS MCARRAOLL SHAW
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Patent number: 6270646Abstract: A metal plating apparatus is described which includes a compressible member having a conductive surface covering substantially all of the surface of the substrate to be plated. The plating current is thereby transmitted over a wide area of the substrate, rather than a few localized contact points. The compressible member is porous so as to absorb the plating solution and transmit the plating solution to the substrate. The wafer and compressible member may rotate with respect to each other. The compressible member may be at cathode potential or may be a passive circuit element.Type: GrantFiled: December 28, 1999Date of Patent: August 7, 2001Assignee: International Business Machines CorporationInventors: Erick Gregory Walton, Dean S. Chung, Lara Sandra Collins, William E. Corbin, Jr., Hariklia Deligianni, Daniel Charles Edelstein, James E. Fluegel, Josef Warren Korejwa, Peter S. Locke, Cyprian Emeka Uzoh
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Patent number: 6181012Abstract: The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses, methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.Type: GrantFiled: April 27, 1998Date of Patent: January 30, 2001Assignee: International Business Machines CorporationInventors: Daniel Charles Edelstein, James McKell Edwin Harper, Chao-Kun Hu, Andrew H. Simon, Cyprian Emeka Uzoh
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Patent number: 6133136Abstract: A structure comprising a layer of copper, a barrier layer, a layer of AlCu, and a pad-limiting layer, wherein the layer of AlCu and barrier layer are interposed between the layer of copper and pad-limiting layer.Type: GrantFiled: May 19, 1999Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Daniel Charles Edelstein, Vincent McGahay, Henry A. Nye, III, Brian George Reid Ottey, William H. Price
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Patent number: 6114937Abstract: High quality factor (Q) spiral and toroidal inductor and transformer are disclosed that are compatible with silicon very large scale integration (VLSI) processing, consume a small IC area, and operate at high frequencies. The spiral inductor has a spiral metal coil deposited in a trench formed in a dielectric layer over a substrate. The metal coil is enclosed in ferromagnetic liner and cap layers, and is connected to an underpass contact through a metal filled via in the dielectric layer. The spiral inductor also includes ferromagnetic cores lines surrounded by the metal spiral coil. A spiral transformer is formed by vertically stacking two spiral inductors, or placing them side-by-side over a ferromagnetic bridge formed below the metal coils and cores lines. The toroidal inductor includes a toroidal metal coil with a core having ferromagnetic strips. The toroidal metal coil is segmented into two coils each having a pair of ports to form a toroidal transformer.Type: GrantFiled: October 14, 1997Date of Patent: September 5, 2000Assignee: International Business Machines CorporationInventors: Joachim Norbert Burghartz, Daniel Charles Edelstein, Christopher Vincent Jahnes, Cyprian Emeka Uzoh