Patents by Inventor Daniel Cutter

Daniel Cutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10691529
    Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Vinodh Gopal, James Guilford, Daniel Cutter, Kirk Yap
  • Patent number: 10528539
    Abstract: In an example, there is disclosed an apparatus, comprising: a data store comprising a hash table having for at least some rows a hash entry indexed by a hash value, and comprising a hash chain of one or more pointers to a history buffer, and a spill counter; and one or more logic elements, including at least one hardware logic element, comprising a data compressor to: inspect a string0 comprising n bytes at position p in a data file; get the spill counter from a hash entry corresponding to string0; inspect a string1 comprising n bytes at p+k, wherein k is a positive integer; get the spill counter from a hash entry corresponding to string1; determine that the spill counter for string1 is less than the spill counter for string0; and search a chain1 (the hash chain of a hash entry corresponding to string1) for a matching string of size at least n+k with an offset of ?k.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Daniel Cutter
  • Publication number: 20200004535
    Abstract: An apparatus and method for loading and storing multiple sets of packed data elements.
    Type: Application
    Filed: June 30, 2018
    Publication date: January 2, 2020
    Inventors: KIRK YAP, JAMES GUILFORD, DANIEL CUTTER, VINODH GOPAL, DANIIL SOKOLOV
  • Publication number: 20190391869
    Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Inventors: Vinodh Gopal, James Guilford, Daniel Cutter, Kirk Yap
  • Patent number: 10270464
    Abstract: An apparatus and method for performing efficient lossless compression.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: James Guilford, Kirk Yap, Vinodh Gopal, Daniel Cutter, Wajdi Feghali
  • Publication number: 20190042611
    Abstract: Technologies for determining unique values include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data, and generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data, generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element. Subsequently, the accelerator device is further to set the corresponding bit-map output bit to indicate a presence of the corresponding element and output the bit-map output table indicative of unique elements that are present in the input data.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 7, 2019
    Inventors: Kirk Yap, James Guilford, Daniel Cutter, Vinodh Gopal
  • Publication number: 20190034490
    Abstract: Technologies for determining set membership include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and definition table configuration data, the input data including a packed unsigned integers of column data from database and the definition table configuration data including a set membership query condition, generate a definition table indicative of element values that satisfy the set membership query condition, generate a lookup request for an element of the column data of the input data, perform the lookup request by accessing the definition table to determine whether the element satisfies the set membership query condition, and generate output indicative of whether the element is a member of the set membership.
    Type: Application
    Filed: December 28, 2017
    Publication date: January 31, 2019
    Inventors: Kirk Yap, James Guilford, Daniel Cutter, Vinodh Gopal
  • Publication number: 20180004744
    Abstract: In an example, there is disclosed an apparatus, comprising: a data store comprising a hash table having for at least some rows a hash entry indexed by a hash value, and comprising a hash chain of one or more pointers to a history buffer, and a spill counter; and one or more logic elements, including at least one hardware logic element, comprising a data compressor to: inspect a string0 comprising n bytes at position p in a data file; get the spill counter from a hash entry corresponding to string0; inspect a string1 comprising n bytes at p+k, wherein k is a positive integer; get the spill counter from a hash entry corresponding to string1; determine that the spill counter for string1 is less than the spill counter for string0; and search a chain1 (the hash chain of a hash entry corresponding to string1) for a matching string of size at least n+k with an offset of ?k.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Daniel Cutter
  • Patent number: 9830285
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Patent number: 9830284
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Patent number: 9824038
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Patent number: 9824037
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Publication number: 20160071558
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Application
    Filed: October 14, 2015
    Publication date: March 10, 2016
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Publication number: 20160070664
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Application
    Filed: October 14, 2015
    Publication date: March 10, 2016
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Publication number: 20160034420
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 4, 2016
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Publication number: 20160019178
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Application
    Filed: July 27, 2015
    Publication date: January 21, 2016
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Patent number: 9128818
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: September 8, 2015
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Publication number: 20150081999
    Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.
    Type: Application
    Filed: May 23, 2014
    Publication date: March 19, 2015
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Patent number: 8738886
    Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
  • Patent number: 8020142
    Abstract: A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: September 13, 2011
    Assignee: Intel Corporation
    Inventors: Gilbert M. Wolrich, William Hasenplaugh, Wajdi Feghali, Daniel Cutter, Vinodh Gopal, Gunnar Gaubatz