Patents by Inventor Daniel Cutter
Daniel Cutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160071558Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: ApplicationFiled: October 14, 2015Publication date: March 10, 2016Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Publication number: 20160034420Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: ApplicationFiled: October 14, 2015Publication date: February 4, 2016Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Publication number: 20160019178Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: ApplicationFiled: July 27, 2015Publication date: January 21, 2016Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 9128818Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: GrantFiled: May 23, 2014Date of Patent: September 8, 2015Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Publication number: 20150081999Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.Type: ApplicationFiled: May 23, 2014Publication date: March 19, 2015Inventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 8738886Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.Type: GrantFiled: February 17, 2004Date of Patent: May 27, 2014Assignee: Intel CorporationInventors: Gilbert Wolrich, Debra Bernstein, Daniel Cutter, Christopher Dolan, Matthew J. Adiletta
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Patent number: 8020142Abstract: A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.Type: GrantFiled: December 14, 2006Date of Patent: September 13, 2011Assignee: Intel CorporationInventors: Gilbert M. Wolrich, William Hasenplaugh, Wajdi Feghali, Daniel Cutter, Vinodh Gopal, Gunnar Gaubatz
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Patent number: 7912886Abstract: The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: GrantFiled: December 14, 2006Date of Patent: March 22, 2011Assignee: Intel CorporationInventors: Vinodh Gopal, Wajdi Feghali, Gilbert M. Wolrich, Daniel Cutter, Robert P. Ottavi
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Patent number: 7730356Abstract: A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2?64) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.Type: GrantFiled: September 28, 2007Date of Patent: June 1, 2010Assignee: Intel CorporationInventors: Vinodh Gopal, John Vranich, Pierre Laurent, Daniel Cutter, Wajdi K. Feghali, Andrew Milne, Erdinc Ozturk
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Patent number: 7607068Abstract: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: GrantFiled: August 31, 2006Date of Patent: October 20, 2009Assignee: Intel CorporationInventors: Vinodh Gopal, Gilbert M. Wolrich, Daniel Cutter, Wajdi Feghali, Robert P. Ottavi
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Publication number: 20090089617Abstract: A method and apparatus for testing mathematical programs where code coverage is exceedingly difficult to hit with random data test vectors (probability <2?64) is provided. To enable testing of the mathematical program, instructions in the mathematical program are trapped. Errors are injected through the use of any status/control flag where an error can be created and be rectified later by a reversible operation so that the result of the mathematical operation is not modified by the injected error.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventors: Vinodh Gopal, John Vranich, Pierre Laurent, Daniel Cutter, Wajdi K. Feghali, Andrew Milne, Erdinc Ozturk
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Publication number: 20080147768Abstract: The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: ApplicationFiled: December 14, 2006Publication date: June 19, 2008Applicant: INTEL CORPORATIONInventors: Vinodh Gopal, Wajdi Feghali, Gilbert Wolrich, Daniel Cutter, Robert P. Ottavi
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Publication number: 20080148011Abstract: The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: ApplicationFiled: December 14, 2006Publication date: June 19, 2008Applicant: INTEL CORPORATIONInventors: Vinodh Gopal, Gilbert M. Wolrich, Gunnar Gaubatz, Daniel Cutter, Wajdi Feghali, Kaan Yuksel, Erdinc Ozturk
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Publication number: 20080148024Abstract: The present disclosure provides a method for instruction processing. The method may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit. The method may further include loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand. The method may also include performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register. The method may further include loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand. The method may additionally include generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD.Type: ApplicationFiled: December 14, 2006Publication date: June 19, 2008Applicant: INTEL CORPORATIONInventors: Gilbert M. Wolrich, William Hasenplaugh, Wajdi Feghali, Daniel Cutter, Vinodh Gopal, Gunnar Gaubatz
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Publication number: 20080059865Abstract: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: INTEL CORPORATIONInventors: Vinodh Gopal, Gilbert M. Wolrich, Daniel Cutter, Wajdi Feghali, Robert P. Ottavi
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Publication number: 20080013715Abstract: In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.Type: ApplicationFiled: December 30, 2005Publication date: January 17, 2008Inventors: Wajdi Feghali, William Hasenplaugh, Gilbert Wolrich, Daniel Cutter, Vinodh Gopal, Gunnar Gaubatz
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Patent number: 7305500Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.Type: GrantFiled: February 10, 2004Date of Patent: December 4, 2007Assignee: Intel CorporationInventors: Matthew J. Adiletta, William Wheeler, James Redfield, Daniel Cutter, Gilbert Wolrich
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Publication number: 20070192571Abstract: In general, in one aspect, the disclosure describes a processing unit that includes a datapath having an input buffer, at least one memory, and an arithmetic logic unit, and control logic having access to a program instruction control store. The control logic controls operation of the datapath and may concurrently cause the datapath to operate in response to different instructions that use different sections of the datapath, wherein the different sections of the datapath comprise a first section transferring data from an input buffer to the memory and a second section transferring data from the memory to the arithmetic logic unit.Type: ApplicationFiled: February 14, 2006Publication date: August 16, 2007Inventors: Wajdi Feghali, William Hasenplaugh, Gilbert Wolrich, Daniel Cutter, Vinodh Gopal, Gunnar Gaubatz
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Publication number: 20070192626Abstract: The disclosure includes description of a processor component that includes a set of register bits to perform a shift register operation. The component window detection logic can detect a window of bits in the set of register bits and, in response to detecting the window, output the window of bits.Type: ApplicationFiled: December 28, 2006Publication date: August 16, 2007Inventors: Wajdi Feghali, William Hasenplaugh, Gilbert Wolrich, Daniel Cutter, Vinodh Gopal, Gunnar Gaubatz
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Publication number: 20070192547Abstract: In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.Type: ApplicationFiled: February 14, 2006Publication date: August 16, 2007Inventors: Wajdi Feghali, William Hasenplaugh, Gilbert Wolrich, Daniel Cutter, Vinodh Gopal