Abstract: In general, in one aspect, a processing unit includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.

Abstract: In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.

Abstract: A video peripheral board for providing video I/O capabilities to a general purpose host computer. The video peripheral board comprises a video I/O port configured to connect a video device, a bus interface circuit, and control logic. The bus interface circuit is configured to connect the video peripheral board into a system bus of the host computer, and is capable of becoming bus master of the system bus. The control logic is configured to control the bus interface circuit to effect transfer of video data between the video I/O port and storage of the host computer, the video data passing through the video I/O port in real time.

Abstract: A video peripheral board for providing video I/O capabilities to a general purpose host computer. The video peripheral board comprises a video I/O port configured to connect a video device, a bus interface circuit, and control logic. The bus interface circuit is configured to connect the video peripheral board into a system bus of the host computer, and is capable of becoming bus master of the system bus. The control logic is configured to control the bus interface circuit to effect transfer of video data between the video I/O port and storage of the host computer, the video data passing through the video I/O port in real time.

Abstract: Apparatus for displaying a reduced-size image in a window of the display of a host computer, the reduced-size image based upon subsampled digital image data. The apparatus includes a host computer and a peripheral controller. The peripheral controller includes a subsampler that receives digital source image data and outputs subsampled image data, and window display circuit. The window display circuit receives a directive from the host computer indicating a window location on the host's display, and the subsampled image data. The window display circuit autonomously (independently of the host CPU) writes the subsampled data through the host's system bus into the display memory at addresses corresponding to the specified window. The apparatus allows video to be displayed on the display screen while avoiding intensive involvement or supervision by the host CPU during display of the video image data.

Abstract: A video peripheral board for providing video I/O capabilities to a general purpose host computer. The video peripheral board comprises a video I/O port configured to connect a video device, a bus interface circuit, and a processor. The bus interface circuit is configured to connect the video peripheral board into a system bus of the host computer, and is capable of becoming bus master of the system bus. The bus interface circuit includes a bus master address generator, a data buffer and bus control logic that provides and receives bus control signals to and from the system bus to effect read and write operations over the system bus independent of the central processing unit of the host computer. The processor controls the bus interface circuit and the video I/O port to effect transfer of video data between the video I/O port and storage of the host computer, the video data passing through the video I/O port in real time.

Abstract: Apparatus for displaying a reduced-size image in a window of the display of a host computer, the reduced-size image based upon subsampled digital image data. The apparatus includes a host computer and a peripheral controller. The peripheral controller includes a subsampler that receives digital source image data and outputs subsampled image data, and window display circuit. The window display circuit receives a directive from the host computer indicating a window location on the host's display, and the subsampled image data. The window display circuit autonomously (independently of the host CPU) writes the subsampled data through the host's system bus into the display memory at addresses corresponding to the specified window. The apparatus allows video to be displayed on the display screen while avoiding intensive involvement or supervision by the host CPU during display of the video image data.