Abstract: An electrical assembly includes a housing at a front side of a panel that extends between mating and receiving ends. The mating end extends through an opening of the panel from the front side to a rear side of the panel. A mounting clip extends between a front end and a rear end and includes a passage therethrough that receives the mating end of the housing. First and second sides of the body define the passage and includes a locking feature extending therefrom the first side into the passage. The clip moves between unlocked and locked positions by sliding the rear end of the clip along the rear side of the panel and the body is flexed outward to allow the locking feature to bypass the housing. The mating end of the housing is coupled with an electrical connector in a locking operation to secure the housing to the panel.

Abstract: A connection system includes a first electrical connector, a second electrical connector, and a mating assist device. The first electrical connector includes a first housing that has a mating end. The second electrical connector includes a second housing that has a mating end. The second housing is a duplicate of the first housing. The mating end of the first housing is configured to mate to the mating end of the second housing during a mating operation. The mating assist device is mounted to the first housing and is configured to engage catch features protruding from an outer surface of the second housing. The mating assist device is configured to be rotated or pivoted relative to both the first and second housings to linearly pull the second electrical connector towards the first electrical connector during the mating operation via the catch features.

Abstract: Dynamic, color-changing surfaces have many applications including but not limited to displays, wearables, and active camouflage. Plasmonic nanostructures can fill this role with the advantages of ultra-small pixels, high reflectivity, and post-fabrication tuning through control of the surrounding media. However, while post-fabrication tuning have yet to cover a full red-green-blue (RGB) color basis set with a single nanostructure of singular dimensions, the present invention contemplates a novel LC-based apparatus and methods that enable such tuning and demonstrates a liquid crystal-plasmonic system that covers the full red/green/blue (RGB) color basis set, as a function only of voltage. This is accomplished through a surface morphology-induced, polarization dependent, plasmonic resonance and a combination of bulk and surface liquid crystal effects that manifest at different voltages.

Abstract: Dynamic, color-changing surfaces have many applications including but not limited to displays, wearables, and active camouflage. Plasmonic nanostructures can fill this role with the advantages of ultra-small pixels, high reflectivity, and post-fabrication tuning through control of the surrounding media. However, while post-fabrication tuning have yet to cover a full red-green-blue (RGB) color basis set with a single nanostructure of singular dimensions, the present invention contemplates a novel LC-based apparatus and methods that enable such tuning and demonstrates a liquid crystal-plasmonic system that covers the full red/green/blue (RGB) color basis set, as a function only of voltage. This is accomplished through a surface morphology-induced, polarization dependent, plasmonic resonance and a combination of bulk and surface liquid crystal effects that manifest at different voltages.

Abstract: Color derived from metallic nanostructures are often more efficient, more robust to environmental changes, and near impossible to damage or bleach due to overexposure. The embodiments combine these advantages with the millisecond re-configurability of liquid crystals to actively control a reflective color of a metallic nanostructure. Of the current technologies that boast active color tunability, many are pigmentation based (e-ink in e-readers) and/or need seconds to change color (photonic ink, electrochromic materials). Speed is an advantage of the embodiments and is comparable to current liquid crystal displays (˜120 Hz). Traditional LC displays use static polymer films (color filters) and white back light to generate color. Being able to actively tune the color from a single metallic nanostructure allows for smaller pixel size, increased resolution, and decreased fabrication cost compared to a conventional RGB color pixel without needing external white light source for extremely low power operations.

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract: A siding system includes a plurality of siding panels having a substrate formed to define a plurality of decorative units. Each of the decorative units includes an average unit distance that is equal to the sum of an average width of the decorative units, and an average width of keyways separating the decorative units. An actual centerline of each of the decorative units is horizontally located within a maximum offset tolerance of a theoretical horizontal center of each of the decorative units. The theoretical horizontal center of each of the decorative units is located at a center location distance measured from a first vertical edge of the substrate. A second siding panel is disposed vertically above a first siding panel when attached to the wall surface. The second siding panel is horizontally offset relative to the first siding panel a panel offset distance.

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract: A semiconductor device includes a substrate, first plural contacts formed in the substrate, a graphene layer formed on the substrate and on the first plural contacts and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts.

Abstract: Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

Abstract: A siding system includes a plurality of siding panels having a substrate formed to define a plurality of decorative units. Each of the decorative units includes an average unit distance that is equal to the sum of an average width of the decorative units, and an average width of keyways separating the decorative units. An actual centerline of each of the decorative units is horizontally located within a maximum offset tolerance of a theoretical horizontal center of each of the decorative units. The theoretical horizontal center of each of the decorative units is located at a center location distance measured from a first vertical edge of the substrate. A second siding panel is disposed vertically above a first siding panel when attached to the wall surface. The second siding panel is horizontally offset relative to the first siding panel a panel offset distance.

Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

Abstract: A semiconductor device includes a substrate, first plural contacts formed in the substrate, a graphene layer formed on the substrate and on the first plural contacts and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts.

Abstract: Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.