Abstract: Improved techniques for accelerated life testing of a sample of semiconductor chips advantageously enable more effective testing and better estimation of lifetime. Full-chip temperature maps are computed at sets of operating and testing conditions. Evaluating the temperature maps enables operations such as: temperature-aware design changes, including adding and/or configuring heating elements, cooling elements, thermal diodes, or sensors; determination of accelerated testing conditions; avoidance of harmful conditions during accelerated testing; and the better estimation of lifetime. Iteration of the computing and the evaluating refines the accelerated testing conditions. Measuring actual testing conditions and computing a full-chip temperature map using the actual testing conditions enables the estimation of lifetime to account for the actual testing conditions. A lifetime acceleration factor map based, at least in part, on the temperature maps is used to produce the estimated lifetime.

Abstract: A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor chip design such that the thermal gradient is normalized by heat dissipated by the supplemental heat source.

Abstract: A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor chip design such that the thermal gradient is normalized by heat dissipated by the supplemental heat source.

Abstract: The present invention is directed to a method of reducing distortions in a pattern disposed on a layer of a substrate, defining a recorded pattern, employing a mold having the pattern recorded therein, defining an original pattern. The method includes, defining a region on the layer in which to produce the recorded pattern. Relative extenuative variations between the substrate and the mold are created to ensure that the original pattern defines an area coextensive with the region. Thereafter, the recorded pattern is formed in the region. The relative extenuative variations are created by heating or cooling of the substrate so that the region defines an area that is slightly smaller/larger than the area of the original pattern. Then compression/tensile forces are applied to the mold to provide the recorded pattern with an area coextensive with the area of the region.

Abstract: The present invention is directed to a method of reducing distortions in a pattern disposed on a layer of a substrate, defining a recorded pattern, employing a mold having the pattern recorded therein, defining an original pattern. The method includes, defining a region on the layer in which to produce the recorded pattern. Relative extenuative variations between the substrate and the mold are created to ensure that the original pattern defines an area coextensive with the region. Thereafter, the recorded pattern is formed in the region. The relative extenuative variations are created by heating or cooling of the substrate so that the region defines an area that is slightly smaller/larger than the area of the original pattern. Then compression/tensile forces are applied to the mold to provide the recorded pattern with an area coextensive with the area of the region.