Patents by Inventor Daniel James Dechene
Daniel James Dechene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977614Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.Type: GrantFiled: September 20, 2021Date of Patent: May 7, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carl Radens, Lawrence A. Clevenger, Daniel James Dechene, Hsueh-Chung Chen
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Publication number: 20240055477Abstract: Embodiments of the invention include a first source region and a first drain region forming a first L-shaped layout. Embodiments include a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate.Type: ApplicationFiled: August 11, 2022Publication date: February 15, 2024Inventors: Ruilong Xie, Nicholas Anthony Lanzillo, Albert M. Chu, DANIEL JAMES DECHENE, Eric Miller, Lawrence A. Clevenger
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Patent number: 11888048Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.Type: GrantFiled: November 9, 2021Date of Patent: January 30, 2024Assignee: International Business Machines CorporationInventors: Shahab Siddiqui, Koji Watanabe, Charlotte DeWan Adams, Kai Zhao, Daniel James Dechene, Rishikesh Krishnan
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Patent number: 11830778Abstract: A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.Type: GrantFiled: November 12, 2020Date of Patent: November 28, 2023Assignee: International Business Machines CorporationInventors: David Wolpert, Daniel James Dechene, Lawrence A. Clevenger, Michael Romain, Somnath Ghosh
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Publication number: 20230369217Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first field-effect transistor (FET) having a first source/drain region is formed. A second FET having a second source/drain region is formed, where the second FET is stacked above the first FET. A trench extending from above the second source/drain region to beneath the first source/drain region is formed, where the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region. A bottom contact is formed in the trench. A dielectric layer is formed in the trench, the dielectric layer on a top surface of the bottom contact. A top contact is formed in the trench, the top contact on a top surface of the dielectric layer.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Inventors: Ruilong Xie, Nicholas Anthony Lanzillo, Julien Frougier, Kangguo Cheng, Eric Miller, Lawrence A. Clevenger, DANIEL JAMES DECHENE
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Publication number: 20230238323Abstract: Interconnect structures including signal lines, power lines and ground lines are configured for improvements in routing and scaling. Vertical stacking of the relatively wide power and ground lines allows for additional signal tracks in the same footprint of a standard cell or other electronic device. Alternatively, vertical stacking of the signal lines allows an increased number of signal tracks. Such interconnect structures are formed during back-end-of-line processing using subtractive or damascene interconnect integration techniques.Type: ApplicationFiled: January 26, 2022Publication date: July 27, 2023Inventors: Christopher J. Penny, Nicholas Anthony Lanzillo, Albert Chu, Ruilong Xie, Lawrence A. Clevenger, DANIEL JAMES DECHENE, Eric Miller, PRASAD BHOSALE
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Publication number: 20230090521Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Carl Radens, Lawrence A. Clevenger, Daniel James Dechene, Hsueh-Chung Chen
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Publication number: 20230029561Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.Type: ApplicationFiled: October 15, 2022Publication date: February 2, 2023Inventors: Kai Zhao, Shahab Siddiqui, Daniel James Dechene, Rishikesh Krishnan, Charlotte DeWan Adams
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Patent number: 11527434Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.Type: GrantFiled: February 20, 2020Date of Patent: December 13, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Mathew Philip, Daniel James Dechene, Somnath Ghosh, Robert Robison
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Patent number: 11515427Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.Type: GrantFiled: June 15, 2020Date of Patent: November 29, 2022Assignee: International Business Machines CorporationInventors: Kai Zhao, Shahab Siddiqui, Daniel James Dechene, Rishikesh Krishnan, Charlotte DeWan Adams
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Publication number: 20220148927Abstract: A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.Type: ApplicationFiled: November 12, 2020Publication date: May 12, 2022Inventors: David Wolpert, DANIEL JAMES DECHENE, Lawrence A. Clevenger, Michael ROMAIN, SOMNATH GHOSH
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Publication number: 20220102153Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.Type: ApplicationFiled: December 9, 2021Publication date: March 31, 2022Inventors: Stuart Sieg, Daniel James Dechene, Eric Miller
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Publication number: 20220069104Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.Type: ApplicationFiled: November 9, 2021Publication date: March 3, 2022Inventors: Shahab Siddiqui, Koji Watanabe, Charlotte DeWan Adams, Kai Zhao, Daniel James Dechene, Rishikesh Krishnan
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Patent number: 11257681Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.Type: GrantFiled: July 17, 2019Date of Patent: February 22, 2022Assignee: International Business Machines CorporationInventors: Stuart Sieg, Daniel James Dechene, Eric Miller
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Patent number: 11211474Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.Type: GrantFiled: January 14, 2020Date of Patent: December 28, 2021Assignee: International Business Machines CorporationInventors: Shahab Siddiqui, Koji Watanabe, Charlotte DeWan Adams, Kai Zhao, Daniel James Dechene, Rishikesh Krishnan
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Publication number: 20210391473Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Kai Zhao, Shahab Siddiqui, Daniel James Dechene, Rishikesh Krishnan, Charlotte DeWan Adams
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Patent number: 11158536Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a hard mask layer on the dielectric layer, forming a sacrificial mandrel layer on the hard mask layer, depositing a sacrificial fill material in an opening in the sacrificial mandrel layer and utilizing the sacrificial fill material to selectively pattern the hard mask layer. The pattern defining first and second spaced openings in the hard mask layer. The method further includes etching the dielectric layer through the first and second openings in the hard mask layer to create first and second trenches in the dielectric layer separated by a dielectric segment of the dielectric layer.Type: GrantFiled: January 7, 2020Date of Patent: October 26, 2021Assignee: International Business Machines CorporationInventors: Daniel James Dechene, Timothy Mathew Philip, Somnath Ghosh, Robert Robison
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Publication number: 20210305152Abstract: A multilayered integrated circuit includes a first layer with a first conductive element overlaying a substrate, a second layer with a second conductive element overlaying the first layer, an intermediate layer between the first layer and the second layer, and a via structure. The via structure is partially embedded within the intermediate layer and is communicatively coupled to the first conductive element and the second conductive element. The via structure extends from the first conductive element and has a first end with a first end width and a second end with a second end width. The second end is further from the substrate than the first end and the first end width is greater than the second end width such that the via structure tapers between the first end and the second end of the via structure.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Inventors: DANIEL JAMES DECHENE, Craig Michael Child, Lawrence A. Clevenger, Kisik Choi, Brent Anderson
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Publication number: 20210296234Abstract: Power distribution fabrics and methods of forming the same include forming a first layer of parallel conductive lines, having a first width. At least one additional layer of conductive lines is formed over the first layer of conductive lines, with the conductive lines of each successive layer in the at least one additional layer having a different orientation and a different width relative to the conductive lines of the preceding layer.Type: ApplicationFiled: March 18, 2020Publication date: September 23, 2021Inventors: Daniel James Dechene, Hsueh-Chung Chen, Lawrence A. Clevenger, Somnath Ghosh, Carl Radens
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Publication number: 20210280457Abstract: Embodiments of the present invention disclose a method and apparatus for making a multi-layer device comprising a conductive layer, a dielectric layer formed on top of conductive layer, a via pattern formed in the dielectric layer, wherein the via pattern is comprised of a plurality of channels and columns, wherein a first portion of the via pattern downwards extends through the entire dielectric layer to directly contact the conductive layer, wherein a second portion of the via pattern extends downwards without coming into direct contact with the conductive layer.Type: ApplicationFiled: March 6, 2020Publication date: September 9, 2021Inventors: Timothy Mathew Philip, Nicholas Anthony Lanzillo, Daniel James Dechene, Robert Robison