Abstract: Silicon-on-insulator (SOI) wafers employing molded substrates to improve insulation and reduce current leakage are provided. In one aspect, a SOI wafer comprises a substrate. An insulating layer (e.g., a buried oxide (BOX) layer) is disposed above the substrate to insulate an active semiconductor layer disposed above the insulating layer, from the substrate. Transistors are formed in the active semiconductor layer. To provide for improved insulation between the active semiconductor layer and the substrate to reduce leakage and improve performance of the active semiconductor layer, the substrate is provided in the form of a molded substrate. A coating layer is also disposed between the molded substrate and the insulating layer of the SOI wafer, in case, for example, the melting temperature of a molding compound used to form the molded substrate is not low enough to prevent contamination of the active semiconductor layer into the insulating layer.

Abstract: A resonator includes a piezoelectric core, a set of electrodes, and at least one ground terminal. The electrodes are arranged on the piezoelectric core and also includes at least one input electrode having a first width and at least one output electrode having a second width that differs from the first width. The ground terminal is also on the piezoelectric core.

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.

Abstract: A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.

Abstract: A pannier mounting system enables a pannier container to be quickly and easily attached to and detached from a rack of a bicycle, motorcycle, or the like. In an embodiment, the system includes a rack attachment bracket that attaches to the rack, a first pair of connectors attached to the bracket, and a second pair of connectors attached to a side of the pannier container. Each of the first pair of connectors includes a magnet, and each of the second pair of connectors includes a magnet. Attraction between magnets of the first pair of connectors and magnets of the second pair of connectors cause the first and second pairs of connectors to align with and connect to one another when brought within close proximity to one another, thereby attaching the pannier container to the bracket. A pannier release handle is used to detach the pannier container from the bracket.

Abstract: An apparatus includes a substrate package and a three dimensional (3D) antenna structure formed in the substrate package. The 3D antenna structure includes multiple substructures to enable the 3D antenna structure to operate as a beam-forming antenna. Each of the multiple substructures has a slanted-plate configuration or a slanted-loop configuration.

Abstract: A filter includes a glass substrate having through substrate vias. The filter also includes capacitors supported by the glass substrate. The capacitors may have a width and/or thickness less than a printing resolution. The filter also includes a 3D inductor within the substrate. The 3D inductor includes a first set of traces on a first surface of the glass substrate coupled to the through substrate vias. The 3D inductor also includes a second set of traces on a second surface of the glass substrate coupled to opposite ends of the through substrate vias. The second surface of the glass substrate is opposite the first surface of the glass substrate. The through substrate vias and traces operate as the 3D inductor. The first set of traces and the second set of traces may also have a width and/or thickness less than the printing resolution.

Abstract: The present application discloses a pad structure that includes a stretchable cuttable material with beveled edge.

Abstract: The present device has at least two chambers for receiving vaporizable components, two heating elements, and circuitry to control heater behavior.

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.

Abstract: An integrated circuit device includes a piezoelectric substrate having a first surface and a second surface opposite the first surface. The device also includes a first electrode and a second electrode on the first surface of the piezoelectric substrate, the first electrode having a first width and the second electrode having a second width. The device further includes a third electrode and a fourth electrode on the second surface of the piezoelectric substrate, the third electrode having a third width that is substantially the same as the second width, and the fourth electrode having a fourth width that is substantially the same as the first width. The first and third electrodes operate as part of a first portion of a microelectromechanical systems (MEMS) resonator, and the second and fourth electrodes operate as part of a second portion of the MEMS resonator.

Abstract: Metal-insulator-metal (MIM) capacitors arranged in a pattern to reduce inductance, and related methods, are disclosed. In one aspect, circuits are provided that employ MIM capacitors coupled in series. The MIM capacitors are arranged in a pattern, wherein a MIM capacitor is placed so as to be electromagnetically adjacent to at least two MIM capacitors, and so that a current of the MIM capacitor flows in a direction opposite or substantially opposite of a direction in which a current of each adjacent MIM capacitor flows. The magnetic field generated at metal connections of each MIM capacitor rotates in an opposite direction of the magnetic field of each electromagnetically adjacent MIM capacitor, and thus a larger proportion of magnetic fields cancel out one another rather than combining, reducing equivalent series inductance (ESL) compared to linear arrangement of MIMs.

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Abstract: An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.