Patents by Inventor Daniel L. Bouvier
Daniel L. Bouvier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210073037Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.Type: ApplicationFiled: September 9, 2019Publication date: March 11, 2021Inventors: Sonu Arora, Daniel L. Bouvier
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Patent number: 10699033Abstract: Systems, apparatuses, and methods for secure enablement of platform features without user intervention are disclosed. In one embodiment, a system includes at least a motherboard and a processor. The motherboard includes at least a socket and an authentication component. The authentication component can be a chipset, expansion I/O device, or other component. The processor is installed in the socket on the motherboard. During a boot sequence, the processor retrieves a key value from the authentication component and then authenticates the key value. Next, the processor determines which one or more features to enable based on the key value. Then, the processor programs one or more feature control registers to enable the one or more features specified by the key value. Accordingly, during normal operation of the system, the one or more features will be enabled.Type: GrantFiled: June 28, 2017Date of Patent: June 30, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Mahesh Subramony, Daniel L. Bouvier
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Publication number: 20190005271Abstract: Systems, apparatuses, and methods for secure enablement of platform features without user intervention are disclosed. In one embodiment, a system includes at least a motherboard and a processor. The motherboard includes at least a socket and an authentication component. The authentication component can be a chipset, expansion I/O device, or other component. The processor is installed in the socket on the motherboard. During a boot sequence, the processor retrieves a key value from the authentication component and then authenticates the key value. Next, the processor determines which one or more features to enable based on the key value. Then, the processor programs one or more feature control registers to enable the one or more features specified by the key value. Accordingly, during normal operation of the system, the one or more features will be enabled.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: Mahesh Subramony, Daniel L. Bouvier
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Patent number: 10170994Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. During operation, the switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of circuits in the set of circuits.Type: GrantFiled: August 22, 2017Date of Patent: January 1, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Thomas J. Gibney, Larry D. Hewitt, Daniel L. Bouvier
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Publication number: 20170371564Abstract: Methods and apparatus monitor memory access activities of non-real-time processing engines to determine time intervals when the memory access activities are low. When such time intervals are found, the methods and apparatus perform burst memory access control for real-time processing engines by bursting data from a memory to a burst memory buffer, or from the burst memory buffer to the memory, to allow fast data access by the real-time processing engines.Type: ApplicationFiled: June 28, 2016Publication date: December 28, 2017Inventors: Shuzhi Hou, Sadagopan Srinivasan, Daniel L. Bouvier
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Patent number: 9342474Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.Type: GrantFiled: July 13, 2015Date of Patent: May 17, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Joseph D. Macri, Daniel L. Bouvier
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Publication number: 20150317269Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.Type: ApplicationFiled: July 13, 2015Publication date: November 5, 2015Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Joseph D. Macri, Daniel L. Bouvier
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Patent number: 9111050Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.Type: GrantFiled: September 16, 2014Date of Patent: August 18, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Joseph D. Macri, Daniel L. Bouvier
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Publication number: 20150006782Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Inventors: Joseph D. Macri, Daniel L. Bouvier
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Patent number: 8856458Abstract: A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol.Type: GrantFiled: December 15, 2009Date of Patent: October 7, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Joseph D. Macri, Daniel L. Bouvier
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Patent number: 8639862Abstract: A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold.Type: GrantFiled: July 21, 2009Date of Patent: January 28, 2014Assignee: Applied Micro Circuits CorporationInventors: Daniel L. Bouvier, Satish Sathe
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Patent number: 8190839Abstract: A multi-processor computer system is provided for managing physical memory domains. The system includes at least one processor having an address interface for sending a memory access message, which includes an address in physical memory and a domain identification (ID). The system also includes a physical memory portioned into a plurality of domains, where each domain includes a plurality of physical addresses. A domain mapping unit (DMU) has an interface to accept the memory access message from the processor. The DMU uses the domain ID to access a permission list, cross-reference the domain ID to a domain including addresses in physical memory, and grant the processor access to the address in response to the address being located in the domain.Type: GrantFiled: March 11, 2009Date of Patent: May 29, 2012Assignee: Applied Micro Circuits CorporationInventor: Daniel L. Bouvier
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Patent number: 8176282Abstract: A system and method are provided for managing cache memory in a computer system. A cache controller portions a cache memory into a plurality of partitions, where each partition includes a plurality of physical cache addresses. Then, the method accepts a memory access message from the processor. The memory access message includes an address in physical memory and a domain identification (ID). A determination is made if the address in physical memory is cacheable. If cacheable, the domain ID is cross-referenced to a cache partition identified by partition bits. An index is derived from the physical memory address, and a partition index is created by combining the partition bits with the index. A processor is granted access (read or write) to an address in cache defined by partition index.Type: GrantFiled: April 6, 2009Date of Patent: May 8, 2012Assignee: Applied Micro Circuits CorporationInventor: Daniel L. Bouvier
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Patent number: 8108571Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.Type: GrantFiled: September 17, 2010Date of Patent: January 31, 2012Assignee: Applied Micro Circuits CorporationInventor: Daniel L. Bouvier
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Publication number: 20110145492Abstract: A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Joseph D. Macri, Daniel L. Bouvier
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Publication number: 20110022871Abstract: A system and method are provided for using queue status to manage power in a system-on-chip (SoC). Messages to be processed are accepted in an SoC with a plurality of selectively enabled processors, and queued. The message traffic can be from an external source via an input/output (IO) interface, or intra-SoC messages between processors. The number of queued messages is monitored and, in response to the number of queued messages exceeding a subscription threshold, one or more processors are enabled. Then, the queued messages are distributed to the enabled processors. Enabling a processor is defined by an action such as supplying power to an unpowered processor, increasing the power supply voltage levels to a processor, increasing the operating frequency of a processor, or a combination of the above-mentioned actions. Likewise, processors can be disabled in response to the number of queued messages falling below the subscription threshold.Type: ApplicationFiled: July 21, 2009Publication date: January 27, 2011Inventors: Daniel L. Bouvier, Satish Sathe
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Patent number: 7849247Abstract: A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.Type: GrantFiled: October 14, 2008Date of Patent: December 7, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Bryan D. Marietta, Michael D. Snyder, Gary L. Whisenhunt, Daniel L. Bouvier
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Patent number: 7822885Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.Type: GrantFiled: October 16, 2007Date of Patent: October 26, 2010Assignee: Applied Micro Circuits CorporationInventor: Daniel L. Bouvier
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Publication number: 20100235598Abstract: A multi-processor computer system is provided for managing physical memory domains. The system includes at least one processor having an address interface for sending a memory access message, which includes an address in physical memory and a domain identification (ID). The system also includes a physical memory portioned into a plurality of domains, where each domain includes a plurality of physical addresses. A domain mapping unit (DMU) has an interface to accept the memory access message from the processor. The DMU uses the domain ID to access a permission list, cross-reference the domain ID to a domain including addresses in physical memory, and grant the processor access to the address in response to the address being located in the domain.Type: ApplicationFiled: March 11, 2009Publication date: September 16, 2010Inventor: Daniel L. Bouvier
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Patent number: 7774522Abstract: A system and method have been provided for pushing cacheable control messages to a processor. The method accepts a first control message, identified as cacheable and addressed to a processor, from a peripheral device. The first control message is allocated into a cache that is associated with the processor, but not associated with the peripheral device. In response to a read-prompt the processor reads the first control message directly from the cache. The read-prompt can be a hardware interrupt generated by the peripheral device referencing the first control message. For example, the peripheral may determine that the first control message has been allocated into the cache and generate a hardware interrupt associated with the first control message. Then, the processor reads the first control message in response to the hardware interrupt read-prompt. Alternately, the read-prompt can be the processor polling the cache for pending control messages.Type: GrantFiled: November 17, 2008Date of Patent: August 10, 2010Assignee: Applied Micro Circuits CorporationInventor: Daniel L. Bouvier