Patents by Inventor Daniel L. Bouvier
Daniel L. Bouvier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100125677Abstract: A system and method have been provided for pushing cacheable control messages to a processor. The method accepts a first control message, identified as cacheable and addressed to a processor, from a peripheral device. The first control message is allocated into a cache that is associated with the processor, but not associated with the peripheral device. In response to a read-prompt the processor reads the first control message directly from the cache. The read-prompt can be a hardware interrupt generated by the peripheral device referencing the first control message. For example, the peripheral may determine that the first control message has been allocated into the cache and generate a hardware interrupt associated with the first control message. Then, the processor reads the first control message in response to the hardware interrupt read-prompt. Alternately, the read-prompt can be the processor polling the cache for pending control messages.Type: ApplicationFiled: November 17, 2008Publication date: May 20, 2010Inventor: Daniel L. Bouvier
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Publication number: 20100095039Abstract: A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.Type: ApplicationFiled: October 14, 2008Publication date: April 15, 2010Inventors: Bryan D. Marietta, Michael D. Snyder, Gary L. Whisenhunt, Daniel L. Bouvier
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Publication number: 20090100200Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.Type: ApplicationFiled: October 16, 2007Publication date: April 16, 2009Inventor: Daniel L. Bouvier
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Patent number: 7106742Abstract: A digital data system employs multiple error protection mechanisms on messages that pass along a link interconnect fabric from one node or device to another node or device. The nodes may be end points (such as processor or storage units), or may be intermediate devices or branch points (such as routers or switches in the interconnect fabric). The interconnect fabric comprises a set of one or more routers, switches, electrical, optical, electroptical or other links along which messages are passed. Messages are packets having a defined format including, e.g., a header portion, typically with source and target addresses, and codes indicating message-type or other information, followed by one or more data or other fields. A first node (“sending” node) of a digital data system as described sends a data transmission comprising one or more message packets to a second node (“receiving” node) over a link of a fabric as described above.Type: GrantFiled: January 11, 2001Date of Patent: September 12, 2006Assignees: Mercury Computer Systems, Inc., Freescale Semiconductor, Inc.Inventors: Robert C. Frisch, Bryan D. Marietta, Daniel L. Bouvier
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Patent number: 7031258Abstract: A digital data system comprises a plurality of links for passing messages between nodes, which may be end points such as memory or processing units, or intermediate or branch points such as routers or other devices in the system. A link level flow control is implemented by control symbols passed between adjacent nodes on a link to efficiently regulate message burden on the link. The control symbols may be embedded within in a message packet to quickly effect control on a link—such as reducing data flow, requesting retransmission of corrupted data, or other intervention—without disruption of the ongoing packet reception. A control symbol may be recognized within the packet by a flag bit, a marker such as a transition in a signal, or a combination of characteristics. The control symbol may be a short word, having a control action identifier code at defined bit positions to indicate the desired link-level control function.Type: GrantFiled: January 11, 2001Date of Patent: April 18, 2006Assignee: Mercury Computer Systems, Inc.Inventors: Robert C. Frisch, Bryan D. Marietta, Daniel L. Bouvier
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Patent number: 6862283Abstract: A data communication system (10) has a plurality of devices (12, 14, 17) which communicate by transmitting information packets having order tags which are processed by an input unit (60) and an output unit (30) in each device. A packet is sent from a transmitting device to a receiving device having an ordering tag wherein both devices are initially order synchronized by starting with the same ordering tag value. Packet transmissions are forced to occur in an order which follows a predetermined ordering of order values which the ordering tags can have. If the receiving device does not receive a packet having the correct order tag value or if a transmission error is detected, the receiving device tells the transmitting device to resend the packet. Any subsequent outstanding transmissions are discarded. Packet ordering and verification occurs at each device-to-device connection.Type: GrantFiled: January 11, 2001Date of Patent: March 1, 2005Assignees: Freescale Semiconductor, Inc., Mercury Computer Systemc, Inc.Inventors: Bryan D. Marietta, Daniel L. Bouvier, Robert C. Frisch
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Patent number: 6804748Abstract: A serial storage architecture (SSA) storage subsystem which includes an SSA initiator and a series of SSA targets which include disk drives housed in a storage pod and an intelligent backplane of the storage pod which houses the other SSA targets. The intelligent backplane includes a controller, a series of status registers, each indicating status of an operating parameter for the SSA target drives, and a series of control registers, each configured to transmit a respective command to selected ones of said SSA target drives. The controller polls each of the status registers and, based on the contents thereof, determines whether an event relating to the operating parameter has occurred. If so, the controller reports the event to the SSA initiator. The SSA initiator may also control the target drives using the control registers.Type: GrantFiled: September 10, 2002Date of Patent: October 12, 2004Assignee: Dell Products L.P.Inventors: Daniel L. Bouvier, Kenneth L. Jeffries
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Patent number: 6678773Abstract: A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol independent. Each of the endpoint devices and the fabric function by specific rules to transfer data having a priority. Within the interconnect, higher priority data transfers take precedence of servicing, and for equal priority data the data is serviced first-in, first-out. Requests of endpoint devices that require a response can not be sent at the highest priority. Endpoint devices may not allow the acceptance of data to be contingent on outputting data of equal or lesser priority than the priority of the incoming data. Transaction priority, ordering and deadlocks are efficiently handled without the interconnect fabric needing to implement a set of bus protocol rules. Within the endpoint devices, additional rules related to ordering may be implemented.Type: GrantFiled: January 11, 2001Date of Patent: January 13, 2004Assignees: Motorola, Inc., Mercury Computer Systems, Inc.Inventors: Bryan D. Marietta, Daniel L. Bouvier, Robert C. Frisch
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Publication number: 20030014587Abstract: A serial storage architecture (SSA) storage subsystem which includes an SSA initiator and a series of SSA targets which include disk drives housed in a storage pod and an intelligent backplane of the storage pod which houses the other SSA targets. The intelligent backplane includes a controller, a series of status registers, each indicating status of an operating parameter for the SSA target drives, and a series of control registers, each configured to transmit a respective command to selected ones of said SSA target drives. The controller polls each of the status registers and, based on the contents thereof, determines whether an event relating to the operating parameter has occurred. If so, the controller reports the event to the SSA initiator. The SSA initiator may also control the target drives using the control registers.Type: ApplicationFiled: September 10, 2002Publication date: January 16, 2003Applicant: Dell USA, L.P.Inventors: Daniel L. Bouvier, Kenneth L. Jeffries
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Patent number: 6505272Abstract: A serial storage architecture (SSA) storage subsystem which includes an SSA initiator and a series of SSA targets which include disk drives housed in a storage pod and an intelligent backplane of the storage pod which houses the other SSA targets. The intelligent backplane includes a controller, a series of status registers, each indicating status of an operating parameter for the SSA target drives, and a series of control registers, each configured to transmit a respective command to selected ones of said SSA target drives. The controller polls each of the status registers and, based on the contents thereof, determines whether an event relating to the operating parameter has occurred. If so, the controller reports the event to the SSA initiator. The SSA initiator may also control the target drives using the control registers.Type: GrantFiled: April 5, 2000Date of Patent: January 7, 2003Assignee: Dell Products L.P.Inventors: Daniel L. Bouvier, Kenneth L. Jeffries
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Publication number: 20010032282Abstract: A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol independent. Each of the endpoint devices and the fabric function by specific rules to transfer data having a priority. Within the interconnect, higher priority data transfers take precedence of servicing, and for equal priority data the data is serviced first-in, first-out. Requests of endpoint devices that require a response can not be sent at the highest priority. Endpoint devices may not allow the acceptance of data to be contingent on outputting data of equal or lesser priority than the priority of the incoming data. Transaction priority, ordering and deadlocks are efficiently handled without the interconnect fabric needing to implement a set of bus protocol rules. Within the endpoint devices, additional rules related to ordering may be implemented.Type: ApplicationFiled: January 11, 2001Publication date: October 18, 2001Inventors: Bryan D. Marietta, Daniel L. Bouvier, Robert C. Frisch
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Publication number: 20010030964Abstract: A data communication system (10) has a plurality of devices (12,14,17) which communicate by transmitting information packets having order tags which are processed by an input unit (60) and an output unit (30) in each device. A packet is sent from a transmitting device to a receiving device having an ordering tag wherein both devices are initially order synchronized by starting with the same ordering tag value. Packet transmissions are forced to occur in an order which follows a predetermined ordering of order values which the ordering tags can have. If the receiving device does not receive a packet having the correct order tag value or if a transmission error is detected, the receiving device tells the transmitting device to resend the packet. Any subsequent outstanding transmissions are discarded. Packet ordering and verification occurs at each device-to-device connection.Type: ApplicationFiled: January 11, 2001Publication date: October 18, 2001Inventors: Bryan D. Marietta, Daniel L. Bouvier, Robert C. Frisch
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Patent number: 6098146Abstract: A serial storage architecture (SSA) storage subsystem which includes an SSA initiator and a series of SSA targets which include disk drives housed in a storage pod and an intelligent backplane of the storage pod which houses the other SSA targets. The intelligent backplane includes a controller, a series of status registers, each indicating status of an operating parameter for the SSA target drives, and a series of control registers, each configured to transmit a respective command to selected ones of said SSA target drives. The controller polls each of the status registers and, based on the contents thereof, determines whether an event relating to the operating parameter has occurred. If so, the controller reports the event to the SSA initiator. The SSA initiator may also control the target drives using the control registers.Type: GrantFiled: April 11, 1997Date of Patent: August 1, 2000Assignee: Dell USA, L. P.Inventors: Daniel L. Bouvier, Kenneth L. Jeffries
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Patent number: 5818206Abstract: A power supply system for detecting an operating configuration of a device, such as a processor, and for providing a corresponding operating voltage to the device. The power supply system includes a configurable power supply receiving configuration signals and for providing an operating voltage having a level corresponding to the configuration signals. A frequency determination circuit, such as a speed jumper block, is provided for asserting a signal indicative of the operating frequency of the device. Also, a device configuration circuit receives a signal indicative of the operating frequency and also receives a signal indicative of a plane configuration of the device, and correspondingly asserts the configuration signals to correspond to one of a matrix or plurality of predetermined operating voltage levels.Type: GrantFiled: April 15, 1996Date of Patent: October 6, 1998Assignee: Dell USA L.P.Inventors: Joshua Titus, Joseph Andrew Vivio, Daniel L. Bouvier