Patents by Inventor Daniel L. Helmick
Daniel L. Helmick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210334041Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones. The storage unit comprises a plurality of dies, where each die comprises two planes. One erase block from each plane of a die is selected for zone formation. Each erase block comprises a plurality of wordlines. A zone comprises one or two dies dedicated to storing parity data and a plurality of dies dedicated to storing user data. The zone further comprises space devoted for controller metadata. The storage device restricts a host device to send write commands in a minimum write size to increase programming efficiency. The minimum write size equals one wordline from one erase block from each plane of each die in the zone dedicated to storing user data minus the space dedicated to metadata.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Applicant: Western Digital Technologies, Inc.Inventors: Alan D. BENNETT, Daniel L. HELMICK, Liam PARKER, Sergey Anatolievich GOROBETS, Peter GRAYSON
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Publication number: 20210334201Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of streams. The storage unit comprises a plurality of dies, where each die comprises two planes. One erase block from each plane of a die is selected for stream formation. Each erase block comprises a plurality of wordlines. A stream comprises one or two dies dedicated to storing parity data and a plurality of dies dedicated to storing user data. The stream further comprises space devoted for controller metadata. The storage device restricts a host device to send write commands in a minimum write size to increase programming efficiency. The minimum write size equals one wordline from one erase block from each plane of each die in the stream dedicated to storing user data minus the space dedicated to metadata.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Applicant: Western Digital Technologies, Inc.Inventors: Alan D. BENNETT, Daniel L. HELMICK, Liam PARKER, Sergey Anatolievich GOROBETS, Peter GRAYSON
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Publication number: 20210334161Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding zone. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding zones. As the parity data is updated, the corresponding command is simultaneously written to the corresponding zone.Type: ApplicationFiled: June 16, 2021Publication date: October 28, 2021Applicant: Western Digital Technologies, Inc.Inventors: Daniel L. HELMICK, Peter GRAYSON, Sergey Anatolievich GOROBETS
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Publication number: 20210333996Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. A first command to write data to a first stream is received, first parity data for the first command is generated in the RAM1, and the data of the first command is written to the first stream. When a second command to write data to a second stream is received, the generated first parity data is copied from the RAM1 to a parking section in the storage unit, and second parity data associated with the second stream is copied from the parking section to the RAM1. The second parity data is updated in the RAM1 with the data of the second command and copied to the parking section.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Applicant: Western Digital Technologies, Inc.Inventors: Sergey Anatolievich GOROBETS, Peter GRAYSON, Daniel L. HELMICK, Liam PARKER
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Publication number: 20210333997Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding stream. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding streams. As the parity data is updated, the corresponding command is simultaneously written to the corresponding stream.Type: ApplicationFiled: April 24, 2020Publication date: October 28, 2021Applicant: Western Digital Technologies, Inc.Inventors: Sergey Anatolievich GOROBETS, Daniel L. HELMICK, Peter GRAYSON
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Publication number: 20210334203Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller, random-access memory (RAM), and a NVM unit, where in the NVM unit comprises a plurality of zones. The RAM unit comprises a logical to physical address (L2P) table for the plurality of zones. The L2P table comprises pointers that are associated with a logical block address (LBA) and the physical location of the data stored in the NVM. The L2P table comprises one pointer per erase block or zone. When a command is received to read data within the NVM, the controller reads the L2P table to determine the LBA and associated pointer of the data. The controller can then determine which zone or erase block the data is stored in, and calculates various offsets of wordlines, pages, and page addresses to find the exact location of the data in the NVM.Type: ApplicationFiled: April 28, 2020Publication date: October 28, 2021Applicant: Western Digital Technologies, Inc.Inventors: Daniel L. HELMICK, Liam PARKER, Alan D. BENNETT, Horst-Christoph Georg HELLWIG
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Publication number: 20210326250Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit divided into a plurality of zones. Data associated with one or more first commands is written to a first portion of a first zone. Upon a predetermined amount of time passing, dummy data is written to a second portion of the first zone to fill the first zone to a zone capacity. Upon receiving one or more second commands to write data, a second zone is allocated and opened, and the data associated with the one or more second commands is written to a first portion of the second zone. The data associated with the one or more first commands is then optionally re-written to a second portion of the second zone to fill the second zone to a zone capacity, and the first zone is erased.Type: ApplicationFiled: April 20, 2020Publication date: October 21, 2021Applicant: Western Digital Technologies, Inc.Inventors: Alan D. BENNETT, Liam PARKER, Daniel L. HELMICK
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Publication number: 20210318833Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of zones, each zone comprises a plurality of erase blocks. Data is written to an erase block of a zone to a program point that is less than the writeable capacity of the erase block. The data in the erase block is associated with various read weights dependent on the location of the data relative to the program point. Data stored closer to the program point has a higher read weight than data stored closer to the beginning of the erase block. The read weights indicate an error susceptibility of the data. When one or more read commands are received, the read weights of the data being read are accumulated to estimate the bit error accumulation until a predetermined value is reached.Type: ApplicationFiled: April 13, 2020Publication date: October 14, 2021Applicant: Western Digital Technologies, Inc.Inventors: Liam PARKER, Daniel L. HELMICK
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Patent number: 11138066Abstract: The A storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. A first command to write data to a first stream is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first stream. When a second command to write data to a second stream is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second stream is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second stream. The updated second XOR data is copied from the RAM1 to the RAM2.Type: GrantFiled: May 27, 2020Date of Patent: October 5, 2021Assignee: Western Digital Technologies, Inc.Inventors: Sergey Anatolievich Gorobets, Daniel L. Helmick, Liam Parker, Alan D. Bennett, Peter Grayson
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Patent number: 11126378Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. The controller restricts the host to a maximum number of zones that can be in the open and active state at a time. Open zones can be switched to the closed state, and vice versa, upon a predetermined amount of time expiring. The maximum number of open zones is based on one or more amounts of time to: generate parity data, copy the parity data from the RAM2 to the RAM1, update the parity data, switch a zone from the open and active state to the closed state, and the amount of space in a temporary RAM1 buffer.Type: GrantFiled: May 27, 2020Date of Patent: September 21, 2021Assignee: Western Digital Technologies, Inc.Inventors: Liam Parker, Daniel L. Helmick, Sergey Anatolievich Gorobets
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Patent number: 11061620Abstract: The present disclosure generally relates to limiting bandwidth in storage devices. One or more bandwidth quality of services levels may be selected and associated with commands according to service level agreements, which may prioritize some commands over others. A storage device fetches and executes one or more the commands. Each of the commands is associated with a bandwidth quality of service level. After executing the commands and transferring the data to a host device, the storage device may delay writing a completion entry corresponding to the executed commands to a completion queue based on the associated bandwidth quality of service level of the commands. The device may then delay revealing the completion entry by delaying updating a completion queue head pointer. The device may further delay sending an interrupt signal to the host device based on the associated bandwidth quality of service level of the commands.Type: GrantFiled: March 27, 2020Date of Patent: July 13, 2021Inventors: Daniel L. Helmick, James Walsh
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Patent number: 11055176Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding zone. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding zones. As the parity data is updated, the corresponding command is simultaneously written to the corresponding zone.Type: GrantFiled: April 24, 2020Date of Patent: July 6, 2021Assignee: Western Digital Technologies, Inc.Inventors: Daniel L. Helmick, Peter Grayson, Sergey Anatolievich Gorobets
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Publication number: 20210132827Abstract: EGs may be combined with ZNSs to offer greater control of how, where and under what configurations, data is stored to various user-defined sections on a SSD. In embodiments, this exposure of control functionalities to an SSD host provides improved performance to data center and other hyperscale users and their clients. In embodiments, larger SSDs may be partitioned into groups of zones for better usage by host devices. In embodiments, the groups may comprise, for example, EGs, sets and MUs, each containing a defined number of zones. In one or more embodiments, hosts may use different EGs to access the device and thereby manage die or channel conflicts in the SSD.Type: ApplicationFiled: May 6, 2020Publication date: May 6, 2021Inventors: Daniel L. HELMICK, Horst-Christoph Georg HELLWIG, Liam PARKER, Ryan R. JONES, Matias BJORLING
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Publication number: 20210089217Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.Type: ApplicationFiled: December 27, 2019Publication date: March 25, 2021Inventors: Matias BJØRLING, Horst-Christoph Georg HELLWIG, David LANDSMAN, Daniel L. HELMICK, Liam PARKER, Alan D. BENNETT, Peter GRAYSON, Judah Gamliel HAHN
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Publication number: 20210081330Abstract: The present disclosure generally relates to methods of operating storage devices. A controller of the storage device is configured to retrieve a first command to write data to one or more first logical blocks of a first zone, and direct memory access (DMA) read and write the data associated with the first command to the first logical blocks. The first logical blocks are between a zone starting point of the first zone and a zone capacity of the first zone. The controller is configured to retrieve a second command to write data to one or more second logical blocks of the first zone, and DMA read and write the data associated with the second command to the second logical blocks. The second logical blocks are between the zone starting and the zone capacity of the first zone, and the first logical blocks are non-sequential to the second logical blocks.Type: ApplicationFiled: December 4, 2019Publication date: March 18, 2021Inventors: Alan D. BENNETT, Matias BJORLING, Daniel L. HELMICK
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Publication number: 20200409589Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The media unit comprises a plurality of dies, and each of the plurality of dies comprising a plurality of erase blocks. The controller is configured to compare an estimated age of a first available erase block in each of the plurality of dies to one another and select one or more of the first available erase blocks from one or more dies of the plurality of dies based on the estimated ages to form a first zone. At least one first available erase block from at least one die of the plurality of die is excluded from the first zone.Type: ApplicationFiled: December 4, 2019Publication date: December 31, 2020Inventors: Alan D. BENNETT, Liam PARKER, Daniel L. HELMICK, Sergey Anatolievich GOROBETS, Peter GRAYSON
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Publication number: 20200409601Abstract: The present disclosure generally relates to methods of operating storage devices. A controller of the storage device retrieves data of a first command a first time and performs a first pass programming of the data of the first command to a first page in a first erase block. Data of a second command is then retrieved a first time by the controller, and the controller performs a first pass programming of the data of the second command to a second page in the first erase block. Upon retrieving the second command, the controller completes the processing of the first command by retrieving the data of the first command a second time and writing the data of the first command to the first page by performing a second pass programming. The data of the first command is stored in the host device until the second pass programming is complete.Type: ApplicationFiled: November 26, 2019Publication date: December 31, 2020Inventors: Daniel L. HELMICK, Peter GRAYSON
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Publication number: 20200341688Abstract: The present disclosure generally presents a method and apparatus to provide a bounded latency, where a device would report “non-service” of a command at the defined system level timeout or earlier if the device was unable to successfully return the data to the host.Type: ApplicationFiled: July 9, 2020Publication date: October 29, 2020Inventors: Neil HUTCHISON, Peter GRAYSON, Xinde HU, Daniel L. HELMICK, Rodney BRITTNER
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Publication number: 20200294616Abstract: A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.Type: ApplicationFiled: May 29, 2020Publication date: September 17, 2020Inventors: Daniel L. HELMICK, Martin V. LUEKER-BODEN
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Patent number: 10770431Abstract: The present disclosure generally relates to storage devices comprising a memory device having a layout optimized for data failure protection. A storage device comprises a memory device having a first package and a second package disposed adjacent to the first package. The first package comprises an even number of memory die having a first storage capacity, and the second package comprises two memory die having a second storage capacity. A first half of the memory dies of the first package and a first memory die of the second package are coupled to a first channel. A second half of the memory dies of the first package and a second memory die of the second package are coupled to a second channel parallel to the first channel.Type: GrantFiled: February 27, 2019Date of Patent: September 8, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Daniel L. Helmick, Kent Anderson