Patents by Inventor Daniel L. Helmick

Daniel L. Helmick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200409589
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The media unit comprises a plurality of dies, and each of the plurality of dies comprising a plurality of erase blocks. The controller is configured to compare an estimated age of a first available erase block in each of the plurality of dies to one another and select one or more of the first available erase blocks from one or more dies of the plurality of dies based on the estimated ages to form a first zone. At least one first available erase block from at least one die of the plurality of die is excluded from the first zone.
    Type: Application
    Filed: December 4, 2019
    Publication date: December 31, 2020
    Inventors: Alan D. BENNETT, Liam PARKER, Daniel L. HELMICK, Sergey Anatolievich GOROBETS, Peter GRAYSON
  • Publication number: 20200341688
    Abstract: The present disclosure generally presents a method and apparatus to provide a bounded latency, where a device would report “non-service” of a command at the defined system level timeout or earlier if the device was unable to successfully return the data to the host.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Inventors: Neil HUTCHISON, Peter GRAYSON, Xinde HU, Daniel L. HELMICK, Rodney BRITTNER
  • Publication number: 20200294616
    Abstract: A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Inventors: Daniel L. HELMICK, Martin V. LUEKER-BODEN
  • Patent number: 10770431
    Abstract: The present disclosure generally relates to storage devices comprising a memory device having a layout optimized for data failure protection. A storage device comprises a memory device having a first package and a second package disposed adjacent to the first package. The first package comprises an even number of memory die having a first storage capacity, and the second package comprises two memory die having a second storage capacity. A first half of the memory dies of the first package and a first memory die of the second package are coupled to a first channel. A second half of the memory dies of the first package and a second memory die of the second package are coupled to a second channel parallel to the first channel.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 8, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Daniel L. Helmick, Kent Anderson
  • Publication number: 20200273841
    Abstract: The present disclosure generally relates to storage devices comprising a memory device having a layout optimized for data failure protection. A storage device comprises a memory device having a first package and a second package disposed adjacent to the first package. The first package comprises an even number of memory die having a first storage capacity, and the second package comprises two memory die having a second storage capacity. A first half of the memory dies of the first package and a first memory die of the second package are coupled to a first channel. A second half of the memory dies of the first package and a second memory die of the second package are coupled to a second channel parallel to the first channel.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Inventors: Daniel L. HELMICK, Kent ANDERSON
  • Publication number: 20200225879
    Abstract: The present disclosure generally relates to limiting bandwidth in storage devices. One or more bandwidth quality of services levels may be selected and associated with commands according to service level agreements, which may prioritize some commands over others. A storage device fetches and executes one or more the commands. Each of the commands is associated with a bandwidth quality of service level. After executing the commands and transferring the data to a host device, the storage device may delay writing a completion entry corresponding to the executed commands to a completion queue based on the associated bandwidth quality of service level of the commands. The device may then delay revealing the completion entry by delaying updating a completion queue head pointer. The device may further delay sending an interrupt signal to the host device based on the associated bandwidth quality of service level of the commands.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Daniel L. HELMICK, James WALSH
  • Patent number: 10679722
    Abstract: A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: June 9, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel L. Helmick, Martin V. Lueker-Boden
  • Publication number: 20180059945
    Abstract: A media controller with response buffer for improved data bus transmissions and method for use therewith are provided. In one embodiment, a storage system is provided comprising a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; and a response buffer configured to store a ready signal sent from the controller after the controller reads data from the plurality of non-volatile memory devices in response to a read command from the host.
    Type: Application
    Filed: October 19, 2016
    Publication date: March 1, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Daniel L. Helmick, Martin V. Lueker-Boden
  • Publication number: 20180059944
    Abstract: A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.
    Type: Application
    Filed: October 19, 2016
    Publication date: March 1, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Daniel L. Helmick, Martin V. Lueker-Boden
  • Publication number: 20180059976
    Abstract: A storage system with integrated components and method for use therewith are provided. In one embodiment, a storage system is provided comprising a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least two of the above components are integrated with each other.
    Type: Application
    Filed: October 19, 2016
    Publication date: March 1, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Daniel L. Helmick, Martin V. Lueker-Boden
  • Publication number: 20180059933
    Abstract: An electrically-buffered NV-DIMM and method for use therewith are provided. In one embodiment, a storage system is provided comprising a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffers.
    Type: Application
    Filed: October 19, 2016
    Publication date: March 1, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Daniel L. Helmick, Martin V. Lueker-Boden
  • Publication number: 20180059943
    Abstract: A media controller and method for management of CPU-attached non-volatile memory are provided. In one embodiment, a storage system is provided comprising a plurality of non-volatile memory devices and a controller in communication with the plurality of non-volatile memory devices. The controller is configured to receive a read command from a host; in response to receiving the read command from the host, read data from the plurality of non-volatile memory devices; perform an operation having an undetermined duration from the host's perspective; send a ready signal to the host after the operation has been performed; receive a send command from the host; and in response to receiving the send command from the host, send the data to the host.
    Type: Application
    Filed: October 19, 2016
    Publication date: March 1, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Martin V. Lueker-Boden, Daniel L. Helmick
  • Patent number: 8780479
    Abstract: A disk drive is disclosed comprising a disk comprising a plurality of tracks, a head attached to a distal end of an actuator arm, and a voice coil motor (VCM) operable to rotate the actuator arm about a pivot bearing including a race and a plurality of ball bearings. The VCM is controlled to execute a first jerk seek in a first radial direction so that the ball bearings slip within the race by a first rotation angle. The VCM is controlled to execute a second jerk seek in the first radial direction so that the ball bearings slip within the race by a second rotation angle, wherein the second rotation angle adds to the first rotation angle in order to rotate the ball bearings relative to the race at a reference angle of the pivot bearing.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 15, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel L. Helmick, Shane Walker, Orhan Beker, Charles D. Richards
  • Patent number: 8767343
    Abstract: A disk drive is disclosed comprising a disk comprising a plurality of data tracks, a head, and control circuitry comprising a servo control system operable to actuate the head over the disk. When an access command is received to access a target data track, a seek operation is initiated to seek the head toward the target data track, wherein the seek operation includes integrating a first state of the servo control system and limiting an output range of the integrating. The output range of the integrating is increased during the seek operation, for example, if an error occurs during the seek operation.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel L. Helmick, Donald Brunnett, Aswartha Narayana, Duc T. Phan