Patents by Inventor Daniel M. Kinzer

Daniel M. Kinzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261519
    Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: March 25, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Marco Giandalia, Jason Zhang, Hongwei Jia, Daniel M. Kinzer
  • Patent number: 12243799
    Abstract: An electronic device includes a substrate and a first gallium nitride (GaN) transistor formed on a first semiconductor die that is electrically coupled to the substrate. A second GaN transistor is formed on a second semiconductor die and is also electrically coupled to the substrate. An integral heat spreader is thermally coupled to the first and the second gallium nitride semiconductor dies and is electrically coupled to the substrate. A first bias voltage is applied to the first GaN transistor via the integral heat spreader and a second bias voltage is applied to the second GaN transistor via the integral heat spreader.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 4, 2025
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Charles Bailley, George Chu, Daniel M. Kinzer
  • Patent number: 12199004
    Abstract: An electronic device includes a substrate and a first gallium nitride (GaN) transistor formed on a first semiconductor die that is electrically coupled to the substrate. A second GaN transistor is formed on a second semiconductor die and is also electrically coupled to the substrate. An integral heat spreader is thermally coupled to the first and the second gallium nitride semiconductor dies and is electrically coupled to the substrate. A first bias voltage is applied to the first GaN transistor via the integral heat spreader and a second bias voltage is applied to the second GaN transistor via the integral heat spreader.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: January 14, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Charles Bailley, George Chu, Daniel M. Kinzer
  • Publication number: 20250015707
    Abstract: An electronic circuit is disclosed. The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, and a gate driver circuit including a pull-down transistor coupled to the gate terminal, and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, where the gate driver circuit is arranged to store energy harvested from the input signal and use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor includes gallium nitride (GaN). In another aspect, the pull-down transistor includes GaN.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Applicant: Navitas Semiconductor Limited
    Inventors: Marco GIANDALIA, Ju Jason ZHANG, Hongwei JIA, Daniel M. KINZER
  • Publication number: 20240421813
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Application
    Filed: June 25, 2024
    Publication date: December 19, 2024
    Applicant: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Publication number: 20240355717
    Abstract: An electronic system is disclosed. The electronic system includes an electronic package having a base with a plurality of external terminals, and further having an electrically insulative material at least partially encapsulating the base, a controller circuit disposed within the electronic package and referenced to a first ground, a first and second driver circuits disposed within the electronic package and referenced to a second ground and arranged to receive isolated control signals from the controller circuit, and a bidirectional switch disposed within the electronic package and referenced to the second ground and arranged to receive drive signals from the first and second driver circuits. In one aspect, the first and second driver circuits are isolated from the controller circuit via capacitors, or magnetics, or optocouplers, or magneto resistors.
    Type: Application
    Filed: April 15, 2024
    Publication date: October 24, 2024
    Applicant: Navitas Semiconductor Limited
    Inventors: Alfred Hesener, Daniel M. Kinzer, Vincent Dessard, Marco Giandalia
  • Patent number: 12119739
    Abstract: An electronic circuit is disclosed. The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, and a gate driver circuit including a pull-down transistor coupled to the gate terminal, and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, where the gate driver circuit is arranged to store energy harvested from the input signal and use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor includes gallium nitride (GaN). In another aspect, the pull-down transistor includes GaN.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: October 15, 2024
    Assignee: Navitas Semiconductor Limited
    Inventors: Marco Giandalia, Jason Zhang, Hongwei Jia, Daniel M. Kinzer
  • Patent number: 12057824
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: August 6, 2024
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Publication number: 20240235531
    Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.
    Type: Application
    Filed: November 17, 2023
    Publication date: July 11, 2024
    Applicant: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Hongwei JIA, Santosh SHARMA, Daniel M. KINZER, Victor SINOW, Matthew Anthony TOPP
  • Publication number: 20240178675
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
    Type: Application
    Filed: December 12, 2023
    Publication date: May 30, 2024
    Applicant: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 11888332
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: January 30, 2024
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 11870429
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: January 9, 2024
    Assignee: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Patent number: 11862996
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: January 2, 2024
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Publication number: 20230421046
    Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Applicant: Navitas Semiconductor Limited
    Inventors: Marco Giandalia, Jason Zhang, Hongwei Jia, Daniel M. Kinzer
  • Patent number: 11855635
    Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: December 26, 2023
    Assignee: Navitas Semiconductor Limited
    Inventors: Hongwei Jia, Santosh Sharma, Daniel M. Kinzer, Victor Sinow, Matthew Anthony Topp
  • Publication number: 20230387067
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Application
    Filed: June 21, 2023
    Publication date: November 30, 2023
    Applicant: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Patent number: 11791709
    Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: October 17, 2023
    Assignee: Navitas Semiconductor Limited
    Inventors: Marco Giandalia, Jason Zhang, Hongwei Jia, Daniel M. Kinzer
  • Patent number: 11770010
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: September 26, 2023
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 11757290
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: September 12, 2023
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 11715720
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: August 1, 2023
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich