Patents by Inventor Daniel M. Kinzer

Daniel M. Kinzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12648207
    Abstract: Field plate structures for gallium nitride (GaN) high voltage transistors are disclosed. In one aspect, a transistor includes a GaN substrate, a source region formed on the GaN substrate, a drain region formed on the GaN substrate and separate from the source region, a gate region formed between the source region and the drain region, a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, and a field plate electrically coupled to the source region, where the field plate extends from a proximal region positioned between the source region and the pedestal, towards the drain region, where at least a portion of the field plate overlaps at least a portion of the pedestal.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: June 2, 2026
    Assignee: Navitas Semiconductor Limited
    Inventors: Pil Sung Park, Daniel M. Kinzer
  • Publication number: 20260046174
    Abstract: A circuit. The circuit includes a first transmitter circuit having a first input terminal arranged to receive a first input data and a first node arranged to transmit a first intermediate data corresponding to the first input data, a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to produce a first output data corresponding to the first input data, a second transmitter circuit including a second input terminal arranged to receive a second input data and the second node that is further arranged to transmit a second intermediate data corresponding to the second input data; and a second receiver circuit including the first node and a second output terminal, the first node further arranged to receive the second intermediate data, and the second output terminal arranged to produce a second output data corresponding to the second input data.
    Type: Application
    Filed: August 7, 2025
    Publication date: February 12, 2026
    Applicant: Navitas Semiconductor Limited
    Inventors: Vincent DESSARD, Aimad SAIB, Stéphane ADRIAENSEN, Xavier BAIE, Daniel M. KINZER, Marco GIANDALIA
  • Publication number: 20260045936
    Abstract: A circuit is disclosed. The circuit includes a modulator circuit referenced to a first ground and arranged to receive at least a first status identifier signal and a second status identifier signal, a pulse width modulated (PWM) signal and a first bitstream signal, and in response generate a modulated signal; an isolation capacitor coupled between to the modulator circuit and a demodulator circuit, wherein the modulator circuit is arranged to transmit the modulated signal through the isolation capacitor to the demodulator circuit; and a clock generator circuit arranged to generate a clock signal (CK0), where the PWM signal and the first bitstream signal are synchronized with CK0; and where the demodulator circuit is referenced to a second ground and is arranged to receive the modulated signal and generate output signals corresponding to the first and second status identifier signals, the PWM signal and the first bitstream signal.
    Type: Application
    Filed: August 7, 2025
    Publication date: February 12, 2026
    Applicant: Navitas Semiconductor Limited
    Inventors: Vincent DESSARD, Aimad SAIB, Stéphane ADRIAENSEN, Xavier BAIE, Daniel M. KINZER, Marco GIANDALIA
  • Publication number: 20250350273
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Application
    Filed: July 23, 2025
    Publication date: November 13, 2025
    Applicant: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. KINZER, Ren Huei Tzeng
  • Patent number: 12439682
    Abstract: Monolithic high side GaN-based circuits using capacitors for level shifting. In one aspect, a power converter includes a GaN-based die, a switch formed on the GaN-based die and having a gate terminal, where the switch is arranged to be selectively conductive according to a driver signal applied to the gate terminal, a buffer circuit formed on the GaN-based die and arranged to receive an input signal and generate a corresponding differential output signal at a first output terminal and at a second output terminal, and a voltage level converter formed on the GaN-based die and having a first input terminal coupled to the first output terminal via a first capacitor and having a second input terminal coupled to the second output terminal via a second capacitor, where the first and second capacitors are formed on the GaN-based die, and the voltage level converter is arranged to generate the driver signal.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: October 7, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Marco Giandalia, Santosh Sharma, Jung Hee Lee, Daniel M. Kinzer
  • Patent number: 12438528
    Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: October 7, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Hongwei Jia, Santosh Sharma, Daniel M. Kinzer, Victor Sinow, Matthew Anthony Topp
  • Patent number: 12401359
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Grant
    Filed: June 25, 2024
    Date of Patent: August 26, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Patent number: 12395093
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: August 19, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Publication number: 20250216883
    Abstract: An electronic device includes a gallium nitride (GaN) substrate having a GaN-based top layer attached to a silicon-based bottom layer, a bidirectional switch formed on the GaN-based top layer and including a first source node, a second source node and a common drain node, a first bias generator circuit arranged to couple the first source node to the silicon-based bottom layer, and a second bias generator circuit arranged to couple the second source node to the silicon-based bottom layer. In one aspect, when a voltage of the first source node is at a higher voltage than the second source node, the first bias generator circuit brings a voltage at the silicon-based bottom layer close to the voltage at the second source node.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Navitas Semiconductor Limited
    Inventors: Ren Huei Tzeng, Daniel M. Kinzer, Santosh Sharma
  • Patent number: 12334421
    Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: June 17, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Jason Zhang, Thomas Ribarich
  • Patent number: 12261519
    Abstract: A circuit is disclosed. The circuit includes a first transistor including a first drain terminal, a first gate terminal and a first source terminal, a depletion-mode transistor including a second drain terminal, a second gate terminal and a second source terminal, the second drain terminal connected to the first drain terminal, the depletion-mode transistor arranged to sense a first voltage at the first drain terminal and generate a second voltage at the second source terminal, and a comparator arranged to receive the second voltage, and transition the first transistor from an on state to an off state in response to the first transistor entering its saturation region of operation. In one aspect, the first transistor includes gallium nitride (GaN). In another aspect, the circuit further includes a logic circuit arranged to receive an output voltage generated by the comparator and to drive the first gate terminal.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: March 25, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Marco Giandalia, Jason Zhang, Hongwei Jia, Daniel M. Kinzer
  • Patent number: 12243799
    Abstract: An electronic device includes a substrate and a first gallium nitride (GaN) transistor formed on a first semiconductor die that is electrically coupled to the substrate. A second GaN transistor is formed on a second semiconductor die and is also electrically coupled to the substrate. An integral heat spreader is thermally coupled to the first and the second gallium nitride semiconductor dies and is electrically coupled to the substrate. A first bias voltage is applied to the first GaN transistor via the integral heat spreader and a second bias voltage is applied to the second GaN transistor via the integral heat spreader.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 4, 2025
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Charles Bailley, George Chu, Daniel M. Kinzer
  • Patent number: 12199004
    Abstract: An electronic device includes a substrate and a first gallium nitride (GaN) transistor formed on a first semiconductor die that is electrically coupled to the substrate. A second GaN transistor is formed on a second semiconductor die and is also electrically coupled to the substrate. An integral heat spreader is thermally coupled to the first and the second gallium nitride semiconductor dies and is electrically coupled to the substrate. A first bias voltage is applied to the first GaN transistor via the integral heat spreader and a second bias voltage is applied to the second GaN transistor via the integral heat spreader.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: January 14, 2025
    Assignee: Navitas Semiconductor Limited
    Inventors: Charles Bailley, George Chu, Daniel M. Kinzer
  • Publication number: 20250015707
    Abstract: An electronic circuit is disclosed. The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, and a gate driver circuit including a pull-down transistor coupled to the gate terminal, and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, where the gate driver circuit is arranged to store energy harvested from the input signal and use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor includes gallium nitride (GaN). In another aspect, the pull-down transistor includes GaN.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Applicant: Navitas Semiconductor Limited
    Inventors: Marco GIANDALIA, Ju Jason ZHANG, Hongwei JIA, Daniel M. KINZER
  • Publication number: 20240421813
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Application
    Filed: June 25, 2024
    Publication date: December 19, 2024
    Applicant: Navitas Semiconductor Limited
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Publication number: 20240355717
    Abstract: An electronic system is disclosed. The electronic system includes an electronic package having a base with a plurality of external terminals, and further having an electrically insulative material at least partially encapsulating the base, a controller circuit disposed within the electronic package and referenced to a first ground, a first and second driver circuits disposed within the electronic package and referenced to a second ground and arranged to receive isolated control signals from the controller circuit, and a bidirectional switch disposed within the electronic package and referenced to the second ground and arranged to receive drive signals from the first and second driver circuits. In one aspect, the first and second driver circuits are isolated from the controller circuit via capacitors, or magnetics, or optocouplers, or magneto resistors.
    Type: Application
    Filed: April 15, 2024
    Publication date: October 24, 2024
    Applicant: Navitas Semiconductor Limited
    Inventors: Alfred Hesener, Daniel M. Kinzer, Vincent Dessard, Marco Giandalia
  • Patent number: 12119739
    Abstract: An electronic circuit is disclosed. The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal, and a gate driver circuit including a pull-down transistor coupled to the gate terminal, and an input terminal arranged to receive an input signal and generate a corresponding output signal at an output terminal coupled to the gate terminal, where the gate driver circuit is arranged to store energy harvested from the input signal and use the stored energy to change a conductive state of the pull-down transistor. In one aspect, the transistor includes gallium nitride (GaN). In another aspect, the pull-down transistor includes GaN.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: October 15, 2024
    Assignee: Navitas Semiconductor Limited
    Inventors: Marco Giandalia, Jason Zhang, Hongwei Jia, Daniel M. Kinzer
  • Patent number: 12057824
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: August 6, 2024
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Publication number: 20240235531
    Abstract: Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.
    Type: Application
    Filed: November 17, 2023
    Publication date: July 11, 2024
    Applicant: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Hongwei JIA, Santosh SHARMA, Daniel M. KINZER, Victor SINOW, Matthew Anthony TOPP
  • Publication number: 20240178675
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
    Type: Application
    Filed: December 12, 2023
    Publication date: May 30, 2024
    Applicant: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang