Abstract: One surface of a metal heat transfer slug contacts the surface of a semiconductor die which contains junction diffusions. The slug and die are molded into a surface mount package which exposes the opposite surface of the slug. Terminal leads are internally connected to the junction diffusions and extended beyond the molded periphery of the package.

Abstract: There is described a process for making a P channel MOS gated device in which N.sup.- bases are first formed through a patterned polysilicon gate structure. A central N.sup.+ contact is then formed in the center of the surface of each N.sup.- base in a second non-critical mask step. A thermal oxide is then grown atop the N.sup.- and N.sup.+ surfaces of each base with differential thickness, the N.sup.+ surface region growing a thicker oxide. A P.sup.+ source implant is then carried out, penetrating only the thinner oxide over the N.sup.- surfaces. Contact openings are then formed in a third mask process and contact metal is deposited in contact with the P.sup.+ and N.sup.+ regions. A ring-shaped termination is simultaneously formed, using the same process steps.

Abstract: A termination structure for a MOSgated device uses a plurality of series-connected lateral P-MOS devices extending in series, from source to drain of the main device. The P-MOS devices are formed in ring fashion around the periphery of the area being terminated. A plurality of concentric spaced P rings diffused into an N type chip termination area are covered by the main device gate oxide which is, in turn, covered with conductive polysilicon to act as a gate for the P-MOS devices so formed. The innermost P ring of each pair of P rings is connected to its gate to prevent turn on of the N channel device. The breakdown voltage of the termination is the sum of the threshold voltage of the P-MOS transistors. A zener diode can be added to the chain to increase the breakdown voltage of the termination.

Abstract: An auxiliary MOSFET is integrated into a lateral IGBT structure with the source and drain of the auxiliary MOSFET in parallel with the emitter-base circuit of the IGBT. A driver, integrated with the IGBT chip, turns off the base emitter voltage to the IGBT before turning off the auxiliary MOSFET during turn off. The auxiliary MOSFET is turned off again at the beginning of the conduction period to ensure full conductivity modulation of the DMOS drain and maximum gain of the PNP transistor. Short circuit protection and overtemperature protection circuits are also integrated into the chip.

Abstract: A process for forming a MOS gated device in which an oxide layer is patterned to have adjacent thick and thin oxide layers atop a silicon surface. Polysilicon is then patterned atop the oxide layer with a critical alignment step to the thin oxide layers in the process. Boron is implanted through both the thick and thin regions of the oxide which are exposed by the polysilicon mask to form P type base regions and P type guard rings in the silicon. Arsenic is thereafter implanted at an energy at which arsenic atoms penetrate only the thin oxide exposed by the polysilicon to form self-aligned source regions in the base regions previously formed. A contact opening mask which is critically aligned to the polysilicon mask forms openings for making contact to the silicon. The device is completed using non-critical alignment masking steps.

Abstract: A depletion mode power MOSFET has a gate electrode formed of material that is refractory, or resistant, to high temperature encountered during device fabrication. A depletion channel region which is formed in a base region of a MOSFET and which interconnects the source and drain regions is formed after a high temperature drive to form the base region, but before a gate oxide and gate and source electrodes are formed at lower temperatures. The depletion channel region is thus subjected to reduced temperatures and grows only slightly in thickness, so that it can be easily depleted. The gate oxide, similarly, is subjected to reduced temperatures, and, particularly when made thin, exhibits high insensitivity to radiation exposure.

Abstract: A process for producing a radiation resistant power MOSFET is disclosed. The gate oxide is formed toward the end of the processing and is not exposed to substantial thermal cycling. Arsenic doping is used in the early part of the process to form the source region, and diffused too slowly to be adversely affected by later thermal cycling process steps. The source region has a relatively high resistance to act as a ballasting resistor to prevent burnout of one of a large number of parallel connected cells.

Abstract: A lateral conduction high power MOSFET chip with integrated control circuits in disclosed for high-side switching applications. A first surface field reduction region disposed between drain and source regions extends from the chip surface and into its body and has a charge density of about 1.times.10.sup.12 ions/cm.sup.2. A second surface field reduction region extends below the first region and the source and drain regions and has a charge density of from about 1.5.times.10.sup.12 to 2.0.times.10.sup.12 ions/cm.sup.2. A substrate extends below the second region and is isolated from both drain and source regions to enable the use of the device as a high-side switch.

Abstract: A photovoltaic isolator consists of a stack of semiconductor wafers which are alloyed together by an aluminum silicon alloy foil. Each of the wafers consists of a very high resistivity P-type body having P+ and N+ diffusions on its opposite surfaces. The wafers are stacked with the same forward conduction polarity. Individual photoisolator stacks are sliced from the completed stack to any desired dimension. Each individual stack is mounted with a light source, preferably an LED, which is arranged to illuminate the edge of each wafer within the stack. The LED and stack are spaced by about 30 mils so that high dielectric isolation exists between the LED and photovoltaic stack. Energization of the LED will produce a relatively high output short circuit current from the stack and a high output voltage which can turn a power MOSFET on very quickly after the energization of the LED.

Abstract: A high power MOSFET is disclosed in which a plurality of hexagonal base regions formed in the surface of a chip receive respective hexagonal annular source regions. The base regions are relatively shallow and of relatively low conductivity material. A central portion of each of the base regions reaches the upper surface of the wafer and contacts a sheet source electrode which also contacts the source regions. The central regions of the base elements which contact the source electrode are of higher conductivity than the main base portion for a distance extending just below the depth of the source regions. The base regions are formed by ion implantation through a gate oxide which is exposed by a window in an overlying polysilicon layer. After ion implantation and driving of the base regions, an annular source region is diffused into each base, employing the same polysilicon window as an outer mask.

Abstract: A bidirectional MOSFET switching circuit employs a pair of common-drain-connected power MOSFETs whose sources are connected to respective nodes for serial connection to a supply-and-load circuit. A gate control circuit provides gate bias for both power MOSFETs from a single gate bias provided between first and second nodes. The gate control circuit includes a pair of common-source-connected control MOSFETs with their sources connected to the first node; with their drains respectively connected to the respective gates of the power MOSFETs; and with their gates connected in common to the second node and to the common-connected drains of the power MOSFETs. The gate bias is preferably provided by a photovoltaic initiator circuit which can be integrated into a monolithic IC along with the power MOSFETs and control circuit.

Abstract: A lateral conduction high power MOSFET chip with integrated control circuits in disclosed for high-side switching applications. A first surface field reduction region disposed between drain and source regions extends from the chip surface and into its body and has a charge density of about 1.times.10.sup.12 ions/cm.sup.2. A second surface field reduction region extends below the first region and the source and drain regions and has a charge density of from about 1.5.times.10.sup.12 to 2.0.times.10.sup.12 ions/cm.sup.2. A substrate extends below the second region and is isolated from both drain and source regions to enable the use of the device as a high-side switch.

Abstract: A high voltage bidirectional output semiconductor field effect transistor (BOSFET) is disclosed which is turned on from the electrical output of a photovoltaic stack which is energized from an LED. The process for manufacture of the device is also disclosed. The BOSFET device consists of two lateral field effect transistors formed in an implanted N(-) region in a P(-) substrate. Two spaced drain regions feed inwardly toward a common N(+) source region separated from the drains by respective P type diffusions. The surface of these diffusions can be inverted by application of voltage to the suitably disposed gate electrode. The depletion field between channel and drain regions is well controlled over the surface of the device. The source contact remains close to the potential of the gate contact at all times so that the device can be used for high voltage switching of either polarity.

Abstract: A high voltage bidirectional output semiconductor field effect transistor (BOSFET) is disclosed which is turned on from the electrical output of a photovoltaic stack which is energized from an LED. The process for manufacture of the device is also disclosed. The BOSFET device consists of two lateral field effect transistors formed in an implanted N(-) region in a P(-) substrate. Two spaced drain regions feed inwardly toward a common N(+) source region separated from the drains by respective P type diffusions. The surface of these diffusions can be inverted by application of voltage to the suitably disposed gate electrode. The depletion field between channel and drain regions is well controlled over the surface of the device. The source contact remains close to the potential of the gate contact at all times so that the device can be used for high voltage switching of either polarity.