Abstract: A III-nitride power semiconductor device that includes a first III-nitride power semiconductor device and a second III-nitride power semiconductor device formed in a common semiconductor die and operatively integrated to form a half-bridge.

Abstract: A Schottky diode is integrated into a planar or trench topology MOSFET having parallel spaced source regions diffused into spaced base stripes. The diffusions forming the source and base stripes are interrupted to permit the drift region to extend to the top of the die and receive a Schottky barrier metal and the source contact. The MOSFET and Schottky share the same drift region, and the pitch between base and source stripes is not changed to receive the Schottky structure.

Abstract: An enhancement mode III-nitride power semiconductor device that includes normally-off channels along the sidewalls of a recess and a process for fabricating the same, the device including a first power electrode, a second power electrode, and a gate disposed between the first power electrode and the second power electrode over at least a sidewall of the recess.

Abstract: A power MOSFET is disclosed in which the source and drain regions are reversed from their usual positions and the drain is on the top of the chip (the surface containing the junction pattern diffusions) and the source is on the bottom of the chip. A plurality of spaced trenches are formed in the top surface. One group of trenches contain gate polysilicon and a gate oxide to control an invertible channel region along the trench. A second group of the trenches have a buried source contact at their bottoms which are connected between the N source material to the P channel region to short out a parasitic bipolar transistor.

Abstract: A plurality of small diameter, closely spaced openings are formed in the back of a semiconductor wafer and are filled with copper plugs in areas of the wafer where the effect of thinning is desired. The openings may be holes of any desired cross-section with a width or diameter of 3 to 5 ?m and a center-to-center spacing of about 50 ?m. The posts can have a depth of 180 ?m or greater in a wafer having a thickness of 200 ?m or greater. The wafer can be silicon, silicon carbide, gallium nitride, or any substrate used for semiconductor device fabrication.

Abstract: A III-nitride power semiconductor device that includes a current sense electrode.

Abstract: A core process is described for the manufacture of a Schottky, MOSFET or Accufet, using a plurality of identical manufacturing steps, including spaced trenches, in a single production line, with the device type to be produced being defined at an implant and diffusion stage for forming very low concentration mesas for a Schottky; higher concentration mesas with source regions for Accufet devices and a channel implant and source implant for a vertical conduction MOSFET.

Abstract: A cellular MOSgated device of planar or trench topology has base injection regions formed between pairs of cells to inject minority carriers to modulate the resistivity of the drift region.

Abstract: A trench type power semiconductor device includes a channel region atop an epitaxially silicon layer and a plurality of shallow gate electrode trenches within the channel region such that the bottom of each trench extends to a distance above the junction defined by the channel region and epitaxially silicon layer. Formed at the bottom of each trench within the channel region are trench tip implants of the same conductivity as the epitaxial silicon layer. The trench tip implants extend through the channel region and into the epitaxially silicon layer. The tips effectively pull up the drift region of the device in a localized fashion. In addition, an insulation layer lines the sidewalls and bottom of each trench such that the insulation layer is thicker along the trench bottoms than along the trench sidewalls. Among other benefits, the shallow trenches, trench tips, and variable trench insulation layer allow for reduced on-state resistance and reduced gate-to-drain charge.

Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Abstract: A substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.

Abstract: A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.

Abstract: A Schottky diode is adjusted by implanting an implant species by way of a titanium silicide Schottky contact and driving the implant species into the underlying silicon substrate by a rapid anneal. The implant is at a low energy, (e.g. about 10 keV) and at a low dose (e.g. less than about 9E12 atoms per cm2) such that the barrier height is slightly increased and the leakage current reduced without forming pn junction and retaining the peak boron concentration in the titanium silicide layer.

Abstract: A power MOSFET has a plurality of spaced rows of parallel coextensive trenches. The trenches are lined with a gate oxide and are filled with conductive polysilicon. Spaced narrow polysilicon strips overlie the silicon surface and connects adjacent trenches to one another. The source contact is made at a location remote from the trenches and between the rows of trenches. The trenches are 1.8 microns deep, are 0.6 microns wide and are spaced by about 0.6 microns or greater. The device has a very low figure of merit and is useful especially in low voltage circuits.

Abstract: A lateral conduction superjunction device has bidirectional conduction characteristics. In a first embodiment, spaced vertical trenches in a P substrate are lined with N diffusions. A central MOSgate structure is disposed centrally in the parallel trenches and source and drain electrodes are at the opposite respective ends of the trenches. In a second embodiment, flat layers of alternately opposite conductivity types have source and drain regions at their opposite ends. A trench MOSgate is disposed between the source region at one end of the layers to enable bidirectional currant flow through the stocked layers.

Abstract: A substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.

Abstract: A lateral conduction superjunction semiconductor device has a plurality of spaced vertical trenches in a junction receiving layer of P− silicon. An N− diffusion lines the walls of the trench and the concentration and thickness of the N− diffusion and P− mesas are arranged to deplete fully in reverse blocking operation. A MOSgate structure is connected at one end of the trenches and a drain is connected at its other end. An N− further layer or an insulation oxide layer may be interposed between a P− substrate and the P− junction receiving layer.

Abstract: A substrate having upper and lower surfaces, the upper surface including a periphery defined by first and second spaced apart side edges and front and rear spaced apart edges; a power semiconductor die disposed on the upper surface of the substrate, the die including a top surface on which at least a first metalized surface is disposed and a bottom surface; a plurality of conductive pads disposed only at the second side edge of the substrate; and a plurality of wire bonds extending from the first metalized surface to the plurality of conductive pads.

Abstract: A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.

Abstract: A lateral conduction superjunction device has bidirectional conduction characteristics. In a first embodiment, spaced vertical trenches in a P substrate are lined with N diffusions. A central MOSgate structure is disposed centrally in the parallel trenches and source and drain electrodes are at the opposite respective ends of the trenches. In a second embodiment, flat layers of alternately opposite conductivity types have source and drain regions at their opposite ends. A trench MOSgate is disposed between the source region at one end of the layers to enable bidirectional currant flow through the stocked layers.