Abstract: Embodiments of the present disclosure are directed to apparatuses, systems, and techniques of a fault resilient transaction handling device for a virtualized system. A request to initiate a transaction involving a direct memory access (DMA) operation to access data associated with one or more guests is received at a device connected to a computing system that hosts the one or more guests. A page fault associated with execution of the DMA operation of the transaction is detected. A transaction fault handling protocol that is to be initiated to address the detected page fault is selected from a set of transaction fault handling protocols. The selected transaction fault handling protocol is caused to be performed to address the detected page fault.

Abstract: A peripheral device includes a bus interface and circuitry. The bus interface is to exchange bus transactions over a peripheral bus that permits out-of-order transfer of at least some of the bus transactions. The circuitry is to generate a plurality of streams of the bus transactions, to select, from among the plurality of streams, one or more streams for which transaction ordering is required, to enforce the transaction ordering among the bus transactions of the selected streams, and to send the bus transactions via the bus interface to the peripheral bus.

Abstract: A data transfer controller connected to a first digital interface of a computer system receives an instruction to prepare a plurality of non-contiguous data elements in a memory of the computer system for transfer to a peripheral device connected to the first digital interface. The data elements are read from the memory of the computer system via a plurality of gather transactions on a second digital interface. The second digital interface is connected to the data transfer controller and the memory. The second digital interface allows for use of a subset of overhead data of the first digital interface for the gather transactions. The data elements are written into a contiguous data block in a buffer. An indication that the contiguous data block is available for transfer from the buffer to the peripheral device via the first digital interface is provided to the peripheral device via the first digital interface.

Abstract: A system is described having one or more processing devices that prepare a work queue entry (WQE), transmit the WQE or provide a doorbell indication indicating the WQE is available, and, in response to determining an execution failure has occurred, perform at least one additional step to facilitate completion of an operation associated with the WQE.

Abstract: A system includes one or more processing devices, one or more peripheral devices, and an interconnection fabric to connect the one or more processing devices and the one or more peripheral devices. A plurality of pairs is set-up in the system, each pair including (i) a respective processing device among the one or more processing devices and (ii) a respective peripheral device among the one or more peripheral devices. Each pair is to communicate over a respective tunnel established via the interconnection fabric, so as to provide resources of the peripheral device to the processing device.

Abstract: A data transfer controller connected to a first digital interface of a computer system receives an instruction to prepare a plurality of non-contiguous data elements in a memory of the computer system for transfer to a peripheral device connected to the first digital interface. The data elements are read from the memory of the computer system via a plurality of gather transactions on a second digital interface. The second digital interface is connected to the data transfer controller and the memory. The second digital interface allows for use of a subset of overhead data of the first digital interface for the gather transactions. The data elements are written into a contiguous data block in a buffer. An indication that the contiguous data block is available for transfer from the buffer to the peripheral device via the first digital interface is provided to the peripheral device via the first digital interface.

Abstract: A peripheral device includes a bus interface and circuitry. The bus interface is to exchange bus transactions over a peripheral bus that permits out-of-order transfer of at least some of the bus transactions. The circuitry is to generate a plurality of streams of the bus transactions, to select, from among the plurality of streams, one or more streams for which transaction ordering is required, to enforce the transaction ordering among the bus transactions of the selected streams, and to send the bus transactions via the bus interface to the peripheral bus.

Abstract: A system includes one or more processors, one or more network devices, and a controller device. The network devices are to exchange communication traffic over a network for the one or more processors, by executing work requests issued by the one or more processors. The controller device is to receive the work requests from the one or more processors and distribute the work requests among the network devices.

Abstract: Various embodiments include techniques for performing memory synchronization operations between processors in a multiprocessor computing system. A first processor transfers data by issuing memory operations to store the data to a shared memory. The first processor issues an asynchronous release operation to a load store unit. In response, the load store unit issues a memory synchronization operation to ensure that the data associated with the memory operations is visible in the shared memory. While the asynchronous release operation is pending, the first processor is able to issue further instructions and perform other operations. When the data associated with the memory operations is visible in the shared memory, the memory synchronization operation completes and the load store unit writes a flag to a separate memory location. Upon detecting that the flag has been written, a second thread, and/or other threads, can reliably read the data stored in the shared memory.

Abstract: A system is described having one or more processing devices that prepare a work queue entry (WQE), transmit the WQE or provide a doorbell indication indicating the WQE is available, and, in response to determining an execution failure has occurred, perform at least one additional step to facilitate completion of an operation associated with the WQE.

Abstract: In one embodiment, a system includes a peripheral data connection bus configured to connect to devices and transfer data between the devices, a scheduling machine configured to connect to the peripheral data connection bus and send a read request message to a first processing device, and the first processing device configured to be connected to the peripheral data connection bus, and responsively to the read request message add a time value to a read response message, and provide the read response message to the scheduling machine, and wherein the scheduling machine is configured to read the time value from the provided read response message and schedule processing of an operation by a second processing device responsively to the read time value.

Abstract: In one embodiment, a system includes a peripheral device including a hardware clock, and processing circuitry to read a given work request entry stored with a plurality of work request entries in at least one work queue in a memory, the given work request entry including timing data and an operator, the timing data being indicative of a time at which a work request should be executed, retrieve a clock value from the hardware clock, and execute the work request with a workload while execution of the work request is timed responsively to the timing data and the operator and the retrieved clock value.

Abstract: A computer based system and method for sending data packets over a data network may include: preparing data packets and packet descriptors on one or more graphical processing units (GPUs); associating packets with a packet descriptor, which may determine a desired transmission time of the packets associated with that descriptor; receiving an indication of a clock time; and physically transmitting packets via an output interface, at a clock time corresponding to the desired transmission time. A computer based system and method for GPU-initiated communication over a 5G data network may include allocating one or more memory buffers in GPU memory; performing at least one 5G signal processing procedure by a GPU; preparing descriptors for a plurality of packets, where each packet includes allocated memory buffers, and where the descriptors provide scheduling instructions for the packets; and triggering the sending of packets over the network based on prepared descriptors.

Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.

Abstract: A system includes one or more processors, and multiple network devices to connect the one or more processors to a network. The one or more processors are to issue work requests to the multiple network devices, by posting work descriptors on one or more shared queues that are each accessible to the multiple network devices. The network devices are to pull the work descriptors from the one or more shared queues, and to execute the work requests responsively to the work descriptors.

Abstract: A system includes multiple network devices and one or more processors. The network devices are to connect to a network. The one or more processors are to exchange communication traffic over the network via the multiple network devices, to estimate multiple communication loads experienced respectively by the multiple network devices, and to distribute subsequent communication traffic among the multiple network devices, responsively to the multiple estimated communication loads.

Abstract: A system is described having one or more processing devices that execute a requestor thread and a doorbell ringing thread. The requestor thread includes receiving a prompt from an application, in response to the prompt, generating a work queue entry (WQE), and after generating the WQE, atomically incrementing a first counter. The doorbell ringing thread includes monitoring a value of a first index, detecting a change in the value of the first index, in response to the change in the value of the first index, generating a control (ctrl) segment using at least one of the value of the first index and a queue number, and ringing a doorbell (DB) by writing the ctrl segment to a control address.

Abstract: A network adapter including a host interface, a network interface, packet processing circuitry, and Translation-as-a-Service (TaaS) circuitry. The host interface is to communicate with a host over a peripheral bus. The network interface is to send and receive packets to and from a network for the host. The packet processing circuitry is to process the packets. The TaaS circuitry is integrated in the network adapter and is to (i) receive from a requesting device a request to translate an input address into a requested address in a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.

Abstract: Various embodiments include techniques for performing memory synchronization operations between processors in a multiprocessor computing system. A first processor transfers data by issuing memory operations to store the data to a shared memory. The first processor issues an asynchronous release operation to a load store unit. In response, the load store unit issues a memory synchronization operation to ensure that the data associated with the memory operations is visible in the shared memory. While the asynchronous release operation is pending, the first processor is able to issue further instructions and perform other operations. When the data associated with the memory operations is visible in the shared memory, the memory synchronization operation completes and the load store unit writes a flag to a separate memory location. Upon detecting that the flag has been written, a second thread, and/or other threads, can reliably read the data stored in the shared memory.

Abstract: A peripheral device includes a bus interface and circuitry. The bus interface is to exchange bus transactions over a peripheral bus that permits out-of-order transfer of at least some of the bus transactions. The circuitry is to generate a plurality of streams of the bus transactions, to select, from among the plurality of streams, one or more streams for which transaction ordering is required, to enforce the transaction ordering among the bus transactions of the selected streams, and to send the bus transactions via the bus interface to the peripheral bus.