Patents by Inventor Daniel Marcovitch
Daniel Marcovitch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11750418Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: GrantFiled: September 7, 2020Date of Patent: September 5, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
-
Publication number: 20230276301Abstract: A computer based system and method for sending data packets over a data network may include: preparing data packets and packet descriptors on one or more graphical processing units (GPUs); associating packets with a packet descriptor, which may determine a desired transmission time of the packets associated with that descriptor; receiving an indication of a clock time; and physically transmitting packets via an output interface, at a clock time corresponding to the desired transmission time. A computer based system and method for GPU-initiated communication over a 5G data network may include allocating one or more memory buffers in GPU memory; performing at least one 5G signal processing procedure by a GPU; preparing descriptors for a plurality of packets, where each packet includes allocated memory buffers, and where the descriptors provide scheduling instructions for the packets; and triggering the sending of packets over the network based on prepared descriptors.Type: ApplicationFiled: June 30, 2022Publication date: August 31, 2023Applicant: NVIDIA CORPORATIONInventors: Sreeram POTLURI, Davide ROSSETTI, Elena AGOSTINI, Pak MARKTHUB, Daniel MARCOVITCH, Sayantan SUR
-
Publication number: 20230251899Abstract: In one embodiment, a system includes a peripheral device including a hardware clock, and processing circuitry to read a given work request entry stored with a plurality of work request entries in at least one work queue in a memory, the given work request entry including timing data and an operator, the timing data being indicative of a time at which a work request should be executed, retrieve a clock value from the hardware clock, and execute the work request with a workload while execution of the work request is timed responsively to the timing data and the operator and the retrieved clock value.Type: ApplicationFiled: February 9, 2022Publication date: August 10, 2023Inventors: Dotan David Levi, Daniel Marcovitch, Natan Manevich, Wojciech Wasko, Igor Voks
-
Publication number: 20230244629Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.Type: ApplicationFiled: February 1, 2022Publication date: August 3, 2023Inventors: Daniel Marcovitch, Dotan David Levi, Eyal Srebro, Eliel Peretz, Roee Moyal, Richard Graham, Gil Bloch, Sean Pieper
-
Publication number: 20230089099Abstract: A processing device includes an interface and one or more processing circuits. The interface is to connect to a host processor. The one or more processing circuits are to receive from the host processor, via the interface, a notification specifying an operation for execution by the processing device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks, in response to the notification, to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation in accordance with the schedule.Type: ApplicationFiled: November 30, 2022Publication date: March 23, 2023Inventors: Roman Nudelman, Gil Bloch, Daniel Marcovitch
-
Publication number: 20230074989Abstract: In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the tinier is activated responsively to a quantity of the multiple missing data packets.Type: ApplicationFiled: November 16, 2022Publication date: March 9, 2023Inventors: Yamin Friedman, Daniel Marcovitch, Gil Levy
-
Patent number: 11556378Abstract: A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a processor. The processing circuitry is configured to receive from the processor, via the host interface, a notification specifying an operation for execution by the network device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks in response to the notification, the processing circuitry is configured to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation is accordance with the schedule.Type: GrantFiled: December 14, 2020Date of Patent: January 17, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Roman Nudelman, Gil Bloch, Daniel Marcovitch
-
Publication number: 20220407824Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry, and retrieve WRs from the multiple NSQs and execute data transmission operations specified in the WRs retrieved from the multiple NSQs.Type: ApplicationFiled: August 31, 2022Publication date: December 22, 2022Inventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Ariel Shahar, Gil Bloch, Lior Narkis
-
Patent number: 11533267Abstract: In one embodiment, a communication apparatus includes a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet.Type: GrantFiled: January 21, 2021Date of Patent: December 20, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Yamin Friedman, Daniel Marcovitch, Gil Levy
-
Publication number: 20220398197Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.Type: ApplicationFiled: July 13, 2022Publication date: December 15, 2022Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks
-
Patent number: 11451493Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.Type: GrantFiled: January 6, 2021Date of Patent: September 20, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Ariel Shahar, Gil Bloch, Lior Narkis
-
Patent number: 11397682Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.Type: GrantFiled: June 30, 2020Date of Patent: July 26, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks
-
Publication number: 20220231957Abstract: In one embodiment, a communication apparatus includes a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet.Type: ApplicationFiled: January 21, 2021Publication date: July 21, 2022Inventors: Yamin Friedman, Daniel Marcovitch, Gil Levy
-
Patent number: 11388263Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.Type: GrantFiled: October 11, 2020Date of Patent: July 12, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Daniel Marcovitch, Lior Narkis, Avi Urman
-
Publication number: 20220217101Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.Type: ApplicationFiled: January 6, 2021Publication date: July 7, 2022Inventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Ariel Shahar, Gil Bloch, Lior Narkis
-
Publication number: 20220188147Abstract: A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a processor. The processing circuitry is configured to receive from the processor, via the host interface, a notification specifying an operation for execution by the network device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks in response to the notification, the processing circuitry is configured to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation is accordance with the schedule.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Inventors: Roman Nudelman, Gil Bloch, Daniel Marcovitch
-
Publication number: 20220116473Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.Type: ApplicationFiled: October 11, 2020Publication date: April 14, 2022Inventors: Dotan David Levi, Daniel Marcovitch, Lior Narkis, Avi Urman
-
Publication number: 20220078043Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: ApplicationFiled: September 7, 2020Publication date: March 10, 2022Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
-
Publication number: 20220029854Abstract: A method in which a plurality of process are configured to hold a block of data destined for other processes, with data repacking circuitry including receiving circuitry configured to receive at least one block of data from a source process of the plurality of processes, the repacking circuitry configured to repack received data in accordance with at least one destination process of the plurality of processes, and sending circuitry configured to send the repacked data to the at least one destination process of the plurality of processes, receiving a set of data for all-to-all data exchange, the set of data being configured as a matrix, the matrix being distributed among the plurality of processes, and transposing the data by each of the plurality of processes sending matrix data from the process to the repacking circuitry, and the repacking circuitry receiving, repacking, and sending the resulting matrix data to destination processes.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Inventors: Richard Graham, Lion Levi, Gil Bloch, Daniel Marcovitch, Noam Bloch, Yong Qin, Yaniv Blumenfeld, Eitan Zahavi
-
Publication number: 20210406179Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.Type: ApplicationFiled: June 30, 2020Publication date: December 30, 2021Inventors: Daniel Marcovitch, Gil Bloch, Richard Graham, Ariel Shahar, Roee Moyal, Igor Voks