Abstract: A power saving improvement in an injection locked oscillator (ILO) used is described. The ILO circuitry comprises a feedback path to provide a finecal (M-bit fine calibration signal). The feedback path need not be active at all times; only when an event occurs that requires the feedback path to update the value of the finecal signal. A monitor is provided to sense the occurrence of such event which may be, for examples, an end of a time period or a predetermined change in temperature. When the event occurs, the feedback path is activated to update the value of the finecal signal.

Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a current-mode logic differential amplifier and a common mode control circuit coupled to the current-mode logic differential amplifier. The common mode control circuit includes a replica circuit replicating a portion of the current-mode logic differential amplifier and a comparator circuit. The comparator circuit is configured to compare a voltage at a sense node in the replica circuit and a reference voltage and to provide to the current-mode logic differential amplifier and, via a feedback loop, to the replica circuit, an output that drives the sense node toward the reference voltage.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.

Abstract: An integrated circuit and a cable interconnect interface are disposed on a substrate and in communication with one another. The cable interconnect interface includes a first plurality of connector pads arranged in a first column and a second plurality of connector pads arranged in a second column. A radio frequency absorption layer is disposed on one or more of the first plurality of connector pads and the second plurality of connector pads. The first plurality of connector pads includes a first group of transmission connector pads and a first group of receiving connector pads. The second plurality of connector pads includes a second group of transmission connector pads and a second group of receiving connector pads. The first group of transmission connector pads is opposite the second group of transmission connector pads, and the first group of receiving connector pads is opposite the second group of receiving connector pads.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.

Abstract: An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Abstract: An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

Abstract: An enhanced quadrature receive serial interface circuit and methods are provided for calibrating the quadrature receive serial interface circuit. A quadrature receive serial interface circuit comprises a first phase rotator and a second phase rotator generating quadrature clocks of identical frequency. Calibration of the quadrature receive serial interface circuit uses a pseudo random bit sequence (PRBS) received by the quadrature receive serial interface circuit. For calibration, one-half of the received PRBS bits are sampled and the phase rotator generating in-phase 0° and 180° clock signals is adjusted to center the data eye for the sampled half of the PRBS bits. Then all data bits (even and odd data bits) of the received PRBS bits are sampled and the phase rotator generating quadrature phase 90° and 270° clock signals is adjusted to center the data eye of all data bits of the PRBS bits to complete calibration.

Abstract: An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.

Abstract: An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

Abstract: A gang drilling machine for drilling a circuit card includes a pair of n and p master drills that are configured to be aligned in registry with respective n and p test vias of the card; pluralities of n and p minion drills that are configured to be aligned in registry with pluralities of n and p live vias of the card; and a controller that is electrically connected to control the n and p master drills and minion drills, and to send and receive electrical signals to and from the card. The controller is configured to: send a query signal to the card; monitor a response signal from the card; determine drilling depth of at least one of the master drills, in response to comparing the response signal to the query signal; and adjust operation of the machine, in response to the determined drilling depth.

Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.

Abstract: Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.

Abstract: A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width.

Abstract: A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width.

Abstract: Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency.

Abstract: Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency.

Abstract: A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance.