Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

Abstract: A method and system for reducing a reflection coefficient below a predetermined value thereby reducing jitter by the variation of the effective impedance of a driver appearing to be bounded during state transitions. The driver may include a pull-up driver and a pull-down driver. In the pull-up driver, the transistors may be switched from a first state to a second state in a staggered fashion where the first state is complementary to the second state; In the pull-down driver, the transistors may be switched from a second state to a first state in a staggered fashion. By staggering the switching of the transistors in the pull-up driver and the pull-down driver, a portion of the current may flow from the pull-up driver to the pull-down driver thereby causing the variation of the effective impedance of the driver to appear to be bounded during state transitions.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A method and apparatus are disclosed for communicating between a master and slave device. A sequence of data sets and a clock signal (“Bus clock”) are sent from the master to the slave, wherein the successive sets are asserted by the master at a certain frequency, each set being asserted for a certain time interval. The data and Bus clock are received by the slave, including capturing the data by the slave, responsive to the received Bus clock. The slave generates, from the received Bus clock, a clock (“Local clock”) for clocking operations on the slave. The sequence of the received data sets is held in a sequence of latches in the slave, each set being held for a time interval that is longer than the certain time interval for which the set was asserted by the master.

Abstract: A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the differential in the first and second output signals.

Abstract: A method and system for reducing a reflection coefficient below a predetermined value thereby reducing jitter by the variation of the effective impedance of a driver appearing to be bounded during state transitions. The driver may comprise a pull-up driver and a pull-down driver. In the pull-driver, the transistors may be switched from a first state to a second state in a staggered fashion where the first state is complementary to the second state. In the pull-down driver, the transistors may be switched from a second state to a first state in a staggered fashion. By staggering the switching of the transistors in the pull-up driver and the pull-down driver, a portion of the current may flow from the pull-up driver to the pull-down driver thereby causing the variation of the effective impedance of the driver to appear to be bounded during state transitions.

Abstract: A method and circuitry for linearly delaying a signal with linear delay steps. In one embodiment, circuitry in an integrated circuit for linearly delaying a signal comprises a plurality of control signals. The circuitry further comprises a fine delay element coupled to at least one of the plurality of control signals where the fine delay element comprises logic circuitry configured to provide fine adjustments to the delay of the signal. The circuitry further comprises at least one course delay element coupled to the fine delay element where the at least one course delay element is coupled to at least one of the plurality of control signals. Furthermore, the at least one course delay element comprises logic circuitry configured to provide course adjustments to the delay of the signal. The circuitry for linearly delaying a signal is configured to provide testability and programmability. The circuitry for linearly delay a signal is configured to provide linear delay steps.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: A data processing system includes a mechanism to periodically idle the normal system operation to allow recalibration of its interface circuitry by transmission of data with transitions and logic levels indicative of actual operation. Provision is made to protect actual data of the system from corruption during recalibration.

Abstract: A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer.

Abstract: A method and apparatus for interface signaling using single-ended and differential data signals improves performance of an interface. A differential pair of data signals and at least one single-ended data signal are transmitted over the interface. The differential pair of data signals is received by a differential receiver and the single-ended data signals are received by a receiver that uses the differential pair of data signals to improve the detection of the single-ended data signal. A novel receiver having a differential input and a single-ended input combines the differential pair of data signals with a single-ended data signal to detect the single-ended data signal providing improved common-mode rejection and reducing the error rate of the single-ended signal. Multiple single-ended signals may be associated with one differential signal, providing a scalable architecture grouping a number of single-ended signals with each differential pair of signals.

Abstract: A method and system for dynamic synchronization of a data processing system processor chips. One of a plurality of chips is designated as a primary chip and all other chips as secondary chips. The clock phase of the chips are synchronized utilizing the primary chip's clock phase as a reference clock phase for the secondary chips.

Abstract: The present invention provides a bus for use in a data processing system. In one embodiment, the bus includes a clock driver, a clock receiver, a plurality of drivers, and a plurality of receivers. The clock receiver is coupled to the clock driver by two clock bus lines carrying complementary clock pulses. Each of the plurality of receivers each coupled to a respective one of the plurality of drivers by bus lines, wherein the receivers detect signals on respective bus lines with respect to a reference voltage derived from a combination of the complementary clock pulses.

Abstract: An improved data driver, method, and system for driving data with an improved slew rate and eye opening is provided. In one embodiment, the data driver includes a non-precompensating data driver and a precompensating data driver. The non-precompensating driver generates a non-precompensating output data pulse corresponding to input data. The non-precompensating data driver generates a pulse in response to every input data bit received. The precompensating driver generates the precompensating pulse only in response to a transition from one data state to a second data state between consecutive data bits. The precompensating data pulse is shorter in duration than the non-precompensating output data. The output data from the data drive is the sum of the non-precompensating output data pulse and the precompensating output data pulse.

Abstract: A method and system for increasing speeds of transferring data in a data transfer system which includes a data source and data sink. Both the data source and data sink include clocks which are synchronized to a common clock frequency. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided within the data sink which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink.

Abstract: A programmable delay element having a fine delay circuit with fractional units of delay. The fine delay circuit has a fine delay circuit with a plurality of selectable delay paths, each delay path having an associated delay interval. The fine delay element is electrically-coupled to a data terminal for receiving and delaying an input signal. A control circuit is electrically-coupled to the fine delay circuit to select the delay path for the input signal. In a further aspect of the invention, the fine delay circuit is electrically-coupled to a coarse delay circuit having a plurality of selectable delay blocks in a repetitive block configuration. The coarse delay circuit is electrically-coupled to a second data terminal for receiving and inserting a second signal through said fine delay circuit. The control circuit is electrically-coupled to the selective delay path of the fine delay circuit and the coarse delay circuit such that either a fine delay, a coarse delay, or a coarse and a fine delay can be selected.

Abstract: A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer.

Abstract: An apparatus for connecting circuit modules is disclosed. The apparatus for connecting circuit modules that receives an input and an output signal at one circuit module and uses a transmitter/receiver to transmit data to and receive data from the second circuit module. Each transmitter/receiver is selectable between a bidirectional mode that transmits and simultaneously receives via two transmission lines, and a unidirectional mode that transmits on a first transmission line and receives from a second transmission line.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.