Patents by Inventor Daniel Murray

Daniel Murray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7371940
    Abstract: The present application relates to an insect resistant transgenic cotton plant. In particular, it relates to a specific event, designated COT102. The application also relates to polynucleotides which are characteristic of the COT102 event, plants comprising said polynucleotides, and methods of detecting the COT102 event. The COT102 event exhibits a novel genotype comprising two expression cassettes. The first cassette comprises a suitable promoter for expression in plants operably linked to a gene that encodes a VIP3A insecticidal toxin, useful in controlling a wide spectrum of lepidopteran insect pests, and a suitable polyadenylation signal. The second cassette comprises a gene which, when expressed, can be used as a selectable marker.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: May 13, 2008
    Assignee: Syngenta Participations AG
    Inventors: Daniel Murray Ellis, David Vincent Negrotto, Liang Shi, Frank Arthur Shotkoski, Carla Randall Thomas
  • Publication number: 20070113060
    Abstract: In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for the SCR. The value includes at least a first encoding that represents an update to a plurality of bits in the SCR, and a first number of bits in the plurality of bits is greater than a second number of bits in the first encoding. The decode circuit is coupled to receive the first encoding from a first storage location responsive to retirement of a first instruction operation assigned to use the first storage location as a destination, and is configured to decode the first encoding and generate the plurality of bits. The decode circuit is configured to update the SCR.
    Type: Application
    Filed: November 17, 2005
    Publication date: May 17, 2007
    Applicant: P.A. Semi, Inc.
    Inventors: Wei-Han Lien, Daniel Murray, Junji Sugisawa
  • Publication number: 20070074091
    Abstract: In one embodiment, a checksum generator comprises an N-bit accumulator and a plurality of N-bit 3:2 carry save adders. A first plurality of the plurality of N-bit 3:2 carry save adders are coupled to receive N-bit inputs extracted from an input to the checksum generator, and one of the first plurality has an N-bit input coupled to the output of the accumulator. A second plurality of the plurality of N-bit 3:2 carry save adders have inputs coupled to outputs of the first plurality, and a most significant bit of each carry output of the first plurality is inserted as a least significant bit of the carry output at the input to the second plurality.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Applicant: P.A. Semi, Inc.
    Inventors: Dominic Go, Daniel Murray
  • Publication number: 20070053522
    Abstract: A listening device and respective method for processing speech audio signals present in noisy acoustical sound waves captured from an adjacent environment for persons with normal hearing. The device comprises a housing for providing acoustical and mechanical coupling to a user's ear, the housing having a first portion for positioning in the ear and an elongated second portion extending from the first portion. The device also comprises a pair of spaced apart microphones positioned on a line-of-sight reference vector and supported by the housing, at least one of the microphones located in the elongated second portion of the housing, the microphones configured for capturing the acoustical sound waves from the environment including speech related elements and non-speech related elements.
    Type: Application
    Filed: September 8, 2005
    Publication date: March 8, 2007
    Inventors: Daniel Murray, Gary Young
  • Publication number: 20070002636
    Abstract: In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method comprises a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
    Type: Application
    Filed: July 1, 2005
    Publication date: January 4, 2007
    Applicant: P.A. Semi, Inc.
    Inventors: Brian Campbell, Vincent von Kaenel, Daniel Murray, Gregory Scott, Sribalan Santhanam
  • Patent number: 7114726
    Abstract: A seal cartridge for a centrifugal pump includes a housing that fits within a conventional stuffing box of the pump and has a cylindrical internal surface receiving the shaft. A pair of annular grooves are provided internally of the housing adjacent respectively opposite ends thereof. Each groove receives an O-ring that runs in contact with the sleeve when the shaft rotates. The sleeve, housing and O-rings define an annular chamber through which water is circulated to cool and lubricate the O-rings. The water is pressurized to cause the O-rings to deform and seal against the sleeve.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: October 3, 2006
    Assignee: AV Cell Inc.
    Inventor: James Daniel Murray
  • Publication number: 20060218515
    Abstract: A method and apparatus are provided for identifying a potential floorplan problem in an integrated circuit layout pattern. The method and apparatus identify a critical timing path in the layout pattern and identify a start point and one or more end points along the timing path. It is then determined whether any of the one or more end points are floor-planned objects. For each end point that is a floor-planned object, the method and apparatus compare a distance between that end point and the start point with a distance threshold to produce a comparison result. A potential floorplan problem can be identified if the distance exceeds the distance threshold.
    Type: Application
    Filed: March 15, 2005
    Publication date: September 28, 2006
    Applicant: LSI Logic Corporation
    Inventors: Jonathan Byrn, Daniel Murray
  • Publication number: 20060170929
    Abstract: A piezoelectric transducer is described that is configured for use within a path length control apparatus of an optical device. The transducer comprises at least one void formed within a central region of the piezoelectric transducer, the one void or alternatively, the multiple voids, utilized at least in part to limit a curvature induced into a mirror during operation of the piezoelectric transducer.
    Type: Application
    Filed: January 28, 2005
    Publication date: August 3, 2006
    Inventors: Christina Schober, Daniel Murray, Danielle Oscarson, Robert Divine
  • Publication number: 20050228846
    Abstract: A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a third circuit coupled to the second circuit and coupled to receive a first operand of the operands to be compared. The first circuit is configured to generate a vector indicative of whether or not bits in the first operand and the second operand are equal. The second circuit receives the vector, and generates an indication of the first bit, beginning with the most significant bit, at which the first operand and the second operand differ. The third circuit receives the indication, and generates an indication of whether or not the first operand is greater than the second operand. In one embodiment, the first, second, and third circuits are included in a combined magnitude compare/count leading zero circuit.
    Type: Application
    Filed: June 7, 2005
    Publication date: October 13, 2005
    Inventor: Daniel Murray
  • Publication number: 20050209913
    Abstract: An internet based method of facilitating commerce between shippers and carriers includes the steps of capturing electronic shipment requests for available shipments, the shipment requests including shipment specific criteria and carrier access criteria, and storing the electronic shipment requests in a database. The electronic shipment requests are presented for action to the remote carriers meeting the carrier access criteria. These remote carriers may reply to the shipment requests with fulfillment offers, which are responsive to the presented shipment requests. Carrier fulfillment offers are received and presented to the remote shippers originating the electronic shipment requests. An Internet based system for implementing the method of the present invention is also disclosed.
    Type: Application
    Filed: May 13, 2005
    Publication date: September 22, 2005
    Inventors: William Wied, Clifford Isaacson, John Thomson, Brian Flint, Diane Dreher, Daniel Murray, Rick MacConnell, John Simpson
  • Publication number: 20050149706
    Abstract: A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.
    Type: Application
    Filed: March 1, 2005
    Publication date: July 7, 2005
    Inventors: David Kruckemyer, Daniel Murray
  • Publication number: 20050144535
    Abstract: Data concerning an occurrence of an interface event affecting a device under test is interpreted by a reference model having a listener registered on a list with the monitor and having like inheritance to the listener interface. The monitor monitors for the occurrence of the interface event and supplies data to the listener in a structure defined by the monitor. An event handler associated with the listener generates a private data structure based on the monitor's data structure concerning the interface event. The private data structure is supplied to the reference model.
    Type: Application
    Filed: December 12, 2003
    Publication date: June 30, 2005
    Inventors: Daniel Murray, George Gorman
  • Publication number: 20040035638
    Abstract: An improved leg attachment apparatus comprising a protective wrap in combination with a leg attachment device that effectively protects a worker's legs from bruising, chaffing, irritation and other negative effects associated with current pole climbing and leg extension devices. In the preferred embodiment, the protective wrap comprises a backing made of cotton, a middle layer of polyfiber material and a securing means in the form of a hook and loop system to fasten the wrap around the leg.
    Type: Application
    Filed: August 20, 2002
    Publication date: February 26, 2004
    Inventor: Daniel Murray Boyd
  • Patent number: 6646340
    Abstract: A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: November 11, 2003
    Assignee: Intel Corporation
    Inventors: Timothy L. Deeter, Thomas Marieb, Daniel Murray, Daniel Pantuso, Sarangapani Sista
  • Publication number: 20030151131
    Abstract: A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.
    Type: Application
    Filed: January 8, 2003
    Publication date: August 14, 2003
    Inventors: Timothy L. Deeter, Thomas Marieb, Daniel Murray, Daniel Pantuso, Sarangapani Sista
  • Patent number: 6525419
    Abstract: A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: February 25, 2003
    Assignee: Intel Corporation
    Inventors: Timothy L. Deeter, Thomas Marieb, Daniel Murray, Daniel Pantuso, Sarangapani Sista
  • Publication number: 20020152499
    Abstract: The invention concerns the location and characterization of a gene (designated NIM1) that is a key component of the SAR pathway and that in connection with chemical and biological inducers enables induction of SAR gene expression and broad spectrum disease resistance in plants. The invention further concerns transformation vectors and processes for overexpressing the NIM1 gene in plants. The transgenic plants thus created have broad spectrum disease resistance.
    Type: Application
    Filed: February 19, 2002
    Publication date: October 17, 2002
    Inventors: John Andrew Ryals, Terrence Patrick Delaney, Leslie Bethards Friedrich, Kristianna Baldwin Weymann, Kay Ann Lawton, Daniel Murray Ellis, Scott Joseph Uknes, Taco Peter Jesse, Pieter Vos
  • Publication number: 20020140177
    Abstract: A seal cartridge for a centrifugal pump includes a housing that fits within a conventional stuffing box of the pump and has a cylindrical internal surface receiving the shaft. A pair of annular grooves are provided internally of the housing adjacent respectively opposite ends thereof. Each groove receives an O-ring that runs in contact with the sleeve when the shaft rotates. The sleeve, housing and O-rings define an annular chamber through which water is circulated to cool and lubricate the O-rings. The water is pressurized to cause the O-rings to deform and seal against the sleeve.
    Type: Application
    Filed: September 26, 2001
    Publication date: October 3, 2002
    Inventor: James Daniel Murray
  • Patent number: 6356943
    Abstract: A distance learning implementation is effected as a client/server solution with a centralized server facility and a remote client facility. The centralized server facility includes a first network with at least one host processor system and associated operating software. Each of the at least one host processor system(s) is configured in the network with at least one specialized apparatus, such as an Integrated Cache Disk Array, which represents an operating environment for purposes of training remote trainees. A gateway, in the form of a router, provides access to the centralized server facility network, and the at least one host processor system is selectably accessible through a switch in the server facility network. A remote training facility network is configured as a client with a minimal amount of hardware to access the centralized server facility network over a standard digital communications network, such as an integrated services digital network (ISDN) line.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: March 12, 2002
    Assignee: EMC Corporation
    Inventors: Daniel Murray, Mark Nugent, Kevin Hunt, Mark Fargnoli
  • Publication number: 20010039568
    Abstract: A distance learning implementation is effected as a client/server solution with a centralized server facility and a remote client facility. The centralized server facility includes a first network with at least one host processor system and associated operating software. Each of the at least one host processor system(s) is configured in the network with at least one specialized apparatus, such as an Integrated Cache Disk Array, which represents an operating environment for purposes of training remote trainees. A gateway, in the form of a router, provides access to the centralized server facility network, and the at least one host processor system is selectably accessible through a switch in the server facility network. A remote training facility network is configured as a client with a minimal amount of hardware to access the centralized server facility network over a standard digital communications network, such as an integrated services digital network (ISDN) line.
    Type: Application
    Filed: December 14, 1998
    Publication date: November 8, 2001
    Inventors: DANIEL MURRAY, MARK NUGENT, KEVIN HUNT, MARK FARGNOLI