Abstract: A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module.

Abstract: The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.

Abstract: A cable having an electrically conducting wire with a cross sectional shape defined by a simple closed curve having from three to eight concave portions separated by an equal number of convex portions. The simple closed curve has no point where the radius of curvature is less than one-sixth (?) of an overall radius of the wire and no point where adjacent curves or lines intersect at an angle. The alternating concave and convex portions of the cable's cross-sectional shape may have substantially the same curvature. The cross-sectional shape of the cable avoids sharp angles and fight curves.

Abstract: A Twinax cable include a first axial cable having an inner diameter portion and an outer diameter portion and including a conductor surrounded by a dielectric material. A second axial cable has an inner diameter portion and an outer diameter portion and including a conductor surrounded by a dielectric material, the second axial cable being arranged such that a portion of the inner diameter thereof contacts the inner diameter portion of the first axial cable. A drain conductor is disposed between at least a portion of the inner diameter portion of the first axial cable and the inner diameter portion of the second axial cable. In addition, the a first foil layer contacts at least a portion of the outer diameter portion of the first axial cable and a second foil layer contacts at least a portion of the outer diameter portion of the second axial cable. An outer foil layer surrounds the first ax cable, the second axial cable, the first foil layer and the second foil layer.

Abstract: The key limiter in a multi-drop system, such as a multi-drop memory system, is the super-positioning of reflection noise from multiple modules or pluggable units, such as DIMMs. Using the noise cancellation approach of the present invention, the noise is distributed across the width of the pulse thus significantly reducing the impact of noise super-positioning. Use of the system of the present invention provides improved noise margins and is a key enabler of high performance, high speed bus, particularly at higher bit rates, as well as an enabler for higher capacity modules, such as DIMMs. The system provides for electrical traces from each of the modules of varying lengths thereby distributing the noise reflections.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory module system and DIMM connector is provided. A DIMM connector includes a plurality of DIMM sockets for receiving a corresponding plurality of DIMMs in a radially oriented, angularly spaced orientation. The DIMM sockets are connected in parallel at a memory module junction so that socket terminals of each DIMM socket are joined to the same relative terminal of all the other DIMM sockets along electronic pathways of substantially equal length. A memory controller selectively communicates with the DIMMs via the DIMM junction. By virtue of the improved topology, impedance within the DIMM connector may be better matched to minimize reflections and improve signal quality.

Abstract: A cable for high speed data communications and method of manufacturing the cable, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers twisted in a rotational direction at a periodic rate along and about a longitudinal axis and conductive shield material wrapped in the rotational direction at the periodic rate along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps at the periodic rate along and about the longitudinal axis.

Abstract: A cable for high speed data communications and methods for manufacturing such cable are disclosed, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer. The cable also includes conductive shield material wrapped in a rotational direction at a rate along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps of the conductive shield material along and about the longitudinal axis, the conductive shield material having a variable width. Transmitting signals on the cable including transmitting a balanced signal characterized by a frequency in the range of 7-9 gigahertz on the cable.

Abstract: The invention is directed to an on-chip probing apparatus. In accordance with an embodiment of the present invention, the on-chip probing apparatus includes: a plurality of switches on a chip; a plurality of externally accessible probe points on the chip; and a multiplexer for controlling the plurality of switches to selectively couple an output signal of the chip to one of the plurality of probe points.

Abstract: An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage.

Abstract: Noise reduction among conductors, the conductors disposed adjacent to one another, the conductors characterized as two or more aggressor conductors and one or more victim conductors, a least two of the aggressor conductors driven with at least two signals that induce unwanted crosstalk upon at least one of the victim conductors, a programmable delay device disposed in a signal path of each of the at least two signals that induce unwanted crosstalk, including programming a delay period into each programmable delay device; receiving, simultaneously at the programmable delay devices, the at least two signals that induce unwanted crosstalk; and transmitting, on two aggressor conductors, the at least two signals that induce unwanted crosstalk, with the at least two signals separated in time by the delay period.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.

Abstract: Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.

Abstract: The present invention is directed to a multi-path redundant architecture for fault tolerant fully buffered dual inline memory modules (FB-DIMMs).

Abstract: A circuit board and a method for fabricating a circuit board are provided. The circuit board includes a dielectric core comprising a first surface and a second surface and a conductive layer comprising a first surface and a second surface. The first surface of the conductive layer is coupled to the second surface of the dielectric core. A first region of the second surface of the conductive layer is smooth and a second region of the second surface of the conductive layer is rough. The first region of the second surface of the conductive layer is operable to support high speed signaling and the second region of the second surface of the conductive layer is operable to support non-high speed signaling.

Abstract: Embodiments of the invention address deficiencies of the art in respect to parameter value configuration for signaling in a multi-drop net, and provide a novel and non-obvious method, system and apparatus for spatial based transceiver adjustment. In one embodiment of the invention, a spatial based dynamic transceiver configuration method can be provided for a multi-drop net. The method can include locating a position for a target receiver for signaling in the multi-drop net, selecting a static transceiver configuration corresponding to the position, and signaling the target receiver utilizing the selected static transceiver configuration. The locating, selecting and signaling can be repeated for different target receivers in different positions in the multi-drop net each repetition utilizing a different selected transceiver configuration.

Abstract: The invention is directed to an on-chip probing apparatus. In accordance with an embodiment of the present invention, the on-chip probing apparatus includes: a plurality of switches on a chip; a plurality of externally accessible probe points on the chip; and a multiplexer for controlling the plurality of switches to selectively couple an output signal of the chip to one of the plurality of probe points.

Abstract: An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.

Abstract: A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.

Abstract: A signal history controlled slew-rate transmission method and bus interface transmitter provide an improved channel equalization mechanism having low complexity. A variable slew-rate feed-forward pre-emphasis circuit changes the slew rate of the applied pre-emphasis in conformity with the history of the transmitted signal. The pre-emphasis circuit may be implemented by a pair of current sources supplying the output of the transmitter, and having differing current values. The current sources are controlled such that upon a signal value change, a high slew rate is provided and when the signal value does not change for two consecutive signal periods, the slew rate is reduced. A current source having a controlled magnitude may be employed to provide a slew rate that changes over time and is continuously reduced until another transmission value change occurs.