Patents by Inventor Daniel Ng

Daniel Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200306479
    Abstract: A vent arrangement is provided to a mask or associated conduit to discharge exhaled gas from the mask to atmosphere. The vent arrangement is structured to diffuse the exhaust vent flow to produce less air jetting, thereby increasing the comfort of the patient and their bed partner. For example, the vent arrangement may include one or more grill components and/or media constructed and arranged to diffuse vent flow.
    Type: Application
    Filed: January 7, 2020
    Publication date: October 1, 2020
    Inventors: Eva NG, Robert Henry FRATER, Lee James VELISS, Barton John KENYON, Daniel Robert JUDSON, Robert Edward HENRY, Alison OLDENBURG, Renee Frances FLOWER, Michael John REID
  • Publication number: 20200263193
    Abstract: Compositions and methods comprising polynucleotides and polypeptides having EPSP (5-enolpyruvylshikimate-3-phosphate) synthase (EPSPS) activity are provided. In specific embodiments, the sequence has an improved property, such as, but not limited to, improved catalytic capacity in the presence of the inhibitor, glyphosate. Further provided are nucleic acid constructs, plants, plant cells, explants, seeds and grain having the EPSPS sequences. Various methods of employing the EPSPS sequences are provided. Such methods include methods for producing a glyphosate tolerant plant, plant cell, explant or seed and methods of controlling weeds in a field containing a crop employing the plants and/or seeds disclosed herein.
    Type: Application
    Filed: March 12, 2020
    Publication date: August 20, 2020
    Applicant: PIONEER HI-BRED INTERNATIONAL, INC.
    Inventors: YUXIA DONG, MICHAEL LASSNER, JIAN LU, EMILY NG, PHILLIP A PATTEN, DANIEL SIEHL
  • Patent number: 10724034
    Abstract: The present application provides a method of synthesizing a genetically-encoded chemical modification of a peptide library. A vector in a substrate, such as a phage, is modified to include a peptide linker and a modification to form a genetic “barcode”. The barcode is screened against potential targets which may be used in drug discovery.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: July 28, 2020
    Inventors: Ratmir Derda, Pavel Kitov, Simon Ng, Katrina Felicia Tjhung, Daniel Ferrer Vinals
  • Patent number: 10686035
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: June 16, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10655141
    Abstract: Compositions and methods comprising polynucleotides and polypeptides having EPSP (5-enolpyruvylshikimate-3-phosphate) synthase (EPSPS) activity are provided. In specific embodiments, the sequence has an improved property, such as, but not limited to, improved catalytic capacity in the presence of the inhibitor, glyphosate. Further provided are nucleic acid constructs, plants, plant cells, explants, seeds and grain having the EPSPS sequences. Various methods of employing the EPSPS sequences are provided. Such methods include methods for producing a glyphosate tolerant plant, plant cell, explant or seed and methods of controlling weeds in a field containing a crop employing the plants and/or seeds disclosed herein.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 19, 2020
    Assignee: PIONEER HI-BRED INTERNATIONAL, INC.
    Inventors: Yuxia Dong, Michael Lassner, Jian Lu, Emily Ng, Phillip A. Patten, Daniel Siehl
  • Patent number: 10608092
    Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
    Type: Grant
    Filed: December 16, 2017
    Date of Patent: March 31, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
  • Patent number: 10557905
    Abstract: Described here are systems and methods for producing high-resolution three-dimensional (“3D”) relaxation parameter maps by calibrating high-resolution 3D magnetic resonance images. As one example, high-resolution longitudinal relaxation time (“T1”) maps can be generated based on images acquired using a T1-weighted pulse sequence, and as another example high-resolution transverse relaxation time (“T2”) maps can be generated based on images acquired using a T2-weighted pulse sequence. The high-resolution images can be calibrated, for example, using a lower resolution single slice relaxation parameter map. The methods described here utilize high-resolution 3D scans and low-resolution relaxation parameter maps that are commonly available on MRI systems. The calibration is a post-processing step used to create the high-resolution 3D relaxation parameter maps from these two types of scans.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: February 11, 2020
    Assignees: Northwestern University, The Board of Trustees of the University of Illinois
    Inventors: Jason Ng, Paras Parikh, Timothy J. Carroll, Daniel C. Lee
  • Patent number: 10543333
    Abstract: A vent arrangement is provided to a mask or associated conduit to discharge exhaled gas from the mask to atmosphere. The vent arrangement is structured to diffuse the exhaust vent flow to produce less air jetting, thereby increasing the comfort of the patient and their bed partner. For example, the vent arrangement may include one or more grill components and/or media constructed and arranged to diffuse vent flow.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: January 28, 2020
    Assignee: ResMed Pty Ltd
    Inventors: Eva Ng, Robert Henry Frater, Lee James Veliss, Barton John Kenyon, Daniel Robert Judson, Robert Edward Henry, Alison Oldenburg, Renee Frances Flower, Michael John Reid
  • Patent number: 10485943
    Abstract: A mask system for delivering air pressurized above atmospheric pressure to the airways of a patient to treat sleep disordered breathing (SDB) by continuous positive airway pressure (CPAP) may include a mask having a cushion configured to form a seal with the patient's nose; two inlet conduits, each of the two inlet conduits configured to extend from a position superior to the patient's head and along a corresponding side of the patient's head, and each of the two inlet conduits being in fluid communication with a corresponding side of the mask to deliver pressurized air to the mask; a first vent arrangement configured to be positioned superior to the patient's head in use and configured to discharge gas to atmosphere during therapy; and a second vent arrangement configured to be positioned inferior to the first vent arrangement in use and configured to discharge gas to atmosphere during therapy.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: November 26, 2019
    Assignee: ResMed Pty Ltd
    Inventors: Eva Ng, Robert Henry Frater, Lee James Veliss, Barton John Kenyon, Daniel Robert Judson, Robert Edward Henry, Alison Oldenburg, Renee Frances Flower, Michael John Reid
  • Patent number: 10449458
    Abstract: The systems and techniques described herein generate a skill rating of a participant with respect to a new title. The system is configured to generate a generic skill rating algorithm based on an aggregate of parameters and parameter weights that already exist in established skill rating algorithms of other titles of a particular game category. Once the generic skill rating algorithm is generated, the system is configured to aggregate, organize, and plug participant performance data into the generic skill rating algorithm so that a representative skill rating for the participant can be calculated. The representative skill rating is provided to the new title thereby enabling the new title to effectively match participants in a multiplayer session of the new title such that a fair and a competitive gaming experience is realized.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 22, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Wisgary Torres, Keith Kline, Daniel Av, Jefferson Ng
  • Publication number: 20190115427
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 18, 2019
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10192982
    Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 29, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
  • Patent number: 10121857
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 6, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Publication number: 20180269293
    Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
    Type: Application
    Filed: December 16, 2017
    Publication date: September 20, 2018
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
  • Publication number: 20180240872
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 23, 2018
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10014381
    Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: July 3, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
  • Patent number: 9960237
    Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: May 1, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Xiaobin Wang, Anup Bhalla, Hamza Yilmaz, Daniel Ng
  • Patent number: 9876096
    Abstract: A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate . A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 ?m to 0.2 ?m.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 23, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Madhur Bobde, Sik Lui, Hamza Yilmaz, Jongoh Kim, Daniel Ng
  • Publication number: 20170373185
    Abstract: A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device includes a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each trench has a first dimension (depth), a a second dimension (width) and a third dimension (length). The body region is of opposite conductivity type to the lightly and heavily doped layers. An opening is formed between first and second trenches through an upper portion of the source region and a body contact region to the body region. A deep implant region of the second conductivity type is formed in the lightly doped layer below the body region. The deep implant region is vertically aligned to the opening and spaced away from a bottom of the opening.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 28, 2017
    Inventors: Hamza Yilmaz, Daniel Ng, Daniel Calafut, Madhur Bobde, Anup Bhalla, Ji Pan, Yeeheng Lee, Jongoh Kim
  • Patent number: 9806175
    Abstract: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: October 31, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Daniel Ng., Tiesheng Li, Sik K. Lui