Patents by Inventor Daniel Prager
Daniel Prager has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8183062Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.Type: GrantFiled: February 24, 2009Date of Patent: May 22, 2012Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager
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Patent number: 8019458Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.Type: GrantFiled: August 6, 2008Date of Patent: September 13, 2011Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
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Patent number: 7967995Abstract: The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures.Type: GrantFiled: March 31, 2008Date of Patent: June 28, 2011Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Radha Sundararajan, Hyung Joo Lee, Daniel Prager, Asao Yamashita
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Patent number: 7899637Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: GrantFiled: June 13, 2007Date of Patent: March 1, 2011Assignee: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Lee Chen, Radha Sundararajan
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Patent number: 7894927Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.Type: GrantFiled: August 6, 2008Date of Patent: February 22, 2011Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
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Patent number: 7713758Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: GrantFiled: June 13, 2007Date of Patent: May 11, 2010Assignee: Tokyo Electon LimitedInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Lee Chen, Radha Sundararajan
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Publication number: 20100036518Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.Type: ApplicationFiled: August 6, 2008Publication date: February 11, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
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Publication number: 20100036514Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.Type: ApplicationFiled: August 6, 2008Publication date: February 11, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
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Publication number: 20090242513Abstract: The invention provides a method of processing a substrate using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more masking layer creation procedures, one or more pre-processing measurement procedures, one or more Partial-Etch (P-E) procedures, one or more Final-Etch (F-E) procedures, and one or more post-processing measurement procedures.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Merritt Funk, Radha Sundararajan, Hyung Joo Lee, Daniel Prager, Asao Yamashita
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Patent number: 7502660Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.Type: GrantFiled: October 2, 2007Date of Patent: March 10, 2009Assignees: International Business Machines Corporation, Tokyo Electron LimitedInventors: David V. Horak, Wesley C. Natzle, Merritt L. Funk, Kevin J. Lally, Daniel Prager
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Publication number: 20080311688Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Radha Sundararajan, Lee Chen
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Publication number: 20080311687Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: TOKYO ELECTRON LIMITEDInventors: Asao Yamashita, Merritt Funk, Daniel Prager, Lee Chen, Radha Sundararajan
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Patent number: 7395132Abstract: To evaluate the adequacy of a profile model, an initial profile model is selected. The profile model includes profile model parameters to be measured in implementing types of process control to be used in controlling a fabrication process. A measurement of profile model parameters is obtained using a first metrology tool and the profile model. A measurement of the profile model parameters is obtained using a second metrology tool and the profile model. Statistical metric criteria are calculated based on the measurements of the profile model parameters obtained using the first and second metrology tools. When the calculated statistical metric criteria are not within matching requirements, the profile model is revised. When the calculated statistical metric criteria are within matching requirements, the profile model or the revised profile model is stored.Type: GrantFiled: May 21, 2007Date of Patent: July 1, 2008Assignee: Timbre Technologies, Inc.Inventors: Daniel Prager, Jason Ferns, Lawrence Lane, Dan Engelhard
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Patent number: 7328418Abstract: This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.Type: GrantFiled: February 1, 2005Date of Patent: February 5, 2008Assignee: Tokyo Electron LimitedInventors: Asao Yamashita, Merritt Funk, Daniel Prager
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Publication number: 20080027577Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.Type: ApplicationFiled: October 2, 2007Publication date: January 31, 2008Inventors: David Horak, Wesley Natzle, Merritt Funk, Kevin Lally, Daniel Prager
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Patent number: 7305322Abstract: To determine the profile of an integrated circuit structure, a signal is measured off the structure with a metrology device. The measured signal is compared to signals in a virtual profile library. The comparison is stopped if matching criteria are met. A subset of a virtual profile data space is determined when the matching criteria are not met. The subset is determined using profile data space associated with the library. A virtual profile signal of the subset is selected. Virtual profile shape/parameters are determined based on the virtual profile signal. A difference is calculated between the measured and virtual profile signals. The difference is compared to virtual profile library creation criteria. If the criteria are met, then the structure is identified using virtual profile data, which includes the virtual profile shape/parameters, associated with the virtual profile signal. Or, if the criteria are not met, then a corrective action is applied.Type: GrantFiled: March 31, 2006Date of Patent: December 4, 2007Assignee: Tokyo Electron LimitedInventors: Merritt Funk, Daniel Prager
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Patent number: 7289864Abstract: A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.Type: GrantFiled: July 12, 2004Date of Patent: October 30, 2007Assignees: International Business Machines Corporation, Tokyo Electron LimitedInventors: David V. Horak, Wesley C. Natzle, Merritt L. Funk, Kevin J. Lally, Daniel Prager
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Publication number: 20070239383Abstract: A method of refining a virtual profile library includes obtaining a reference signal measured off a reference structure on a semiconductor wafer with a metrology device. A best match is selected of the reference signal in a virtual profile data space. The virtual profile data space has data points with specified accuracy values. The data points represent virtual profile parameters and associated virtual profile signals. The virtual profile parameters characterize the profile of an integrated circuit structure. The best match being a data point of the profile data space with a signal closest to the reference signal. Refined virtual profile parameters are determined corresponding to the reference signal based on the virtual profile parameters of the selected virtual profile signal using a refinement procedure.Type: ApplicationFiled: March 31, 2006Publication date: October 11, 2007Applicant: Tokyo Electron, Ltd.Inventors: Merritt Funk, Daniel Prager
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Publication number: 20070237383Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, or mask data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: ApplicationFiled: March 28, 2006Publication date: October 11, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle
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Publication number: 20070238201Abstract: A method of processing a wafer is presented that includes creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated structure on the wafer, metrology data for at least one nested structure on the wafer, bi-layer mask data, and BARC layer data. At least one pre-processing prediction map is calculated for the wafer. A pre-processing confidence map is calculated for the wafer. The pre-processing confidence map includes a set of confidence data for the plurality of dies on the wafer. A prioritized measurement site is determined when the confidence data for one or more dies is not within the confidence limits. A new measurement recipe that includes the prioritized measurement site is then created.Type: ApplicationFiled: March 28, 2006Publication date: October 11, 2007Inventors: Merritt Funk, Radha Sundararajan, Daniel Prager, Wesley Natzle