Patents by Inventor Daniel Rivas

Daniel Rivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10992550
    Abstract: Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 27, 2021
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan, Mark A. Schmisseur, Steen Larsen
  • Patent number: 10970216
    Abstract: An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Kshitij A. Doshi, Francesc Guim Bernat, Daniel Rivas Barragan, Suraj Prabhakaran
  • Patent number: 10949313
    Abstract: A network controller, including: a processor; and a resource permission engine to: provision a composite node including a processor and a first disaggregated compute resource (DCR) remote from the processor, the first DCR to access a target resource; determine that the first DCR has failed; provision a second DCR for the composite node, the second DCR to access the target resource; and instruct the target resource to revoke a permission for the first DCR and grant the permission to the second DCR.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Daniel Rivas Barragan, Patrick Lu
  • Patent number: 10924721
    Abstract: Apparatus, systems, methods, and articles of manufacture are disclosed for assigning a color to a point in three-dimensional (3D) video. An example system includes an aggregator to access data from real cameras, the data including spatial coordinates and colors for a plurality of two-dimensional (2D) points in video data captured by the real cameras. The aggregator is to create a point cloud correlating the 2D points to the 3D points. The example system also includes a selector to select a subset of the real cameras based on a position of a virtual camera. In addition, the example system includes an analyzer to: select a point from the point cloud in a field of view of the virtual camera; select one of the subset of real cameras having a non-occluded view of the point and a perspective closest to that of the virtual camera; and assign a color to the point based on color data associated with the selected one of the real cameras.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Daniel Rivas Perpen, Diego Prilusky
  • Patent number: 10873521
    Abstract: Techniques for fast startup for composite nodes in software-defined infrastructures (SDI) are described. A SDI system may include an SDI manager component, including one or more processor circuits to access one or more remote resources, the SDI manager component may including a node manager to determine, based upon one or more reservation tables stored in a non-transitory computer-readable storage medium, an initial set of resources for creating the composite node from among the one or more remote resources. The partition manager may create the composite node using the initial set of resources, the initial set of resources is a subset of resources required by the composite node. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: December 22, 2020
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Susanne M. Balle, Daniel Rivas Barragan, John Chun Kwok Leung, Suraj Prabhakaran, Murugasamy K. Nachimuthu, Slawomir Putyrski
  • Patent number: 10833969
    Abstract: Techniques for increasing malleability in software-defined infrastructures are described. A compute node, including one or more processor circuits, may be configured to access one or more remote resources via a fabric, the compute node may be configured to monitor utilization of the one or more remote resources. The compute node may be further configured to identify based on one or more criteria that one or more remote resources may be released and initiate release of identified one or more remote resources. The compute node may be configured to generate a notification to a software stack indicating that the identified one or more remote resources has been released. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: November 10, 2020
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Susanne M. Balle, Daniel Rivas Barragan, John Chun Kwok Leung, Suraj Prabhakaran, Murugasamy K. Nachimuthu, Slawomir Putyrski
  • Patent number: 10824358
    Abstract: Technologies for dynamically managing the reliability of disaggregated resources in a managed node include a resource manager server. The resource manager server includes communication circuit to receive resource data from a set of disaggregated resources that indicates reliability of each disaggregated resource of the set of disaggregated resources and a node request to compose a managed node. The resource manager server further includes a compute engine to determine node parameters from the node request indicative of a target reliability of one or more disaggregated resources of the set of disaggregated resources to be included in the managed node, compose a managed node from the set of disaggregated resources that satisfies the node parameters by configuring the compute sled to utilize the disaggregated resources of the managed node for the execution of a workload, and monitor the disaggregated resources of the managed node for a failure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Murugasamy K. Nachimuthu, Daniel Rivas Barragan
  • Publication number: 20200304425
    Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan, Alejandro Duran Gonzalez
  • Patent number: 10785295
    Abstract: Fabric encapsulated resilient storage is hardware-assisted resilient storage in which the reliability capabilities of a storage server are abstracted and managed transparently by a host fabric interface (HFI) to a switch. The switch abstracts the reliability capabilities of a storage server into a level of resilience in a hierarchy of levels of resilience. The resilience levels are accessible by clients as a quantifiable characteristic of the storage server. The resilience levels are used by the switch fabric to filter which storage servers store objects responsive to client requests to store objects at a specified level of resilience.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Daniel Rivas Barragan, Kshitij A. Doshi, Mark A. Schmisseur, Steen Larsen
  • Patent number: 10754588
    Abstract: Technology for a controller in a storage area network (SAN) node operable to perform data requests is described. The controller can receive a data request from a remote node. The data request can specify a data payload and a type of operation associated with the data request. The controller can select a kernel from a kernel table stored in the memory based on a set of rules. The kernel can be matched to the data request in accordance with the set of rules. The kernel can be configured using a bit stream. The controller can execute the kernel in order to perform the data request in accordance with the data payload and the type of operation.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan
  • Patent number: 10728311
    Abstract: A computing device, method and system to implement an adaptive compression scheme in a network fabric. The computing device may include a memory device and a fabric controller coupled to the memory device. The fabric controller may include processing circuitry having logic to communicate with a plurality of peer computing devices in the network fabric. The logic may be configured to implement the adaptive compression scheme to select, based on static information and on dynamic information relating to a peer computing device of the plurality of peer computing devices, a compression algorithm to compress a data payload destined for the peer computing device, and to compress the data payload based on the compression algorithm. The static information may include information on data payload decompression supported methods of the peer computing device, and the dynamic information may include information on link load at the peer computing device.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Francesc Guim Bernat, Thomas Willhalm, Nicolas A. Salhuana, Daniel Rivas Barragan
  • Patent number: 10686688
    Abstract: Techniques for reducing fragmentation in software-defined infrastructures are described. A compute node, including one or more processor circuits, may be configured to access one or more remote resources via a fabric, the compute node may be configured to receive a dynamic tolerated fragmentation for the one or more remote resources. The compute node may be configured to monitor the performance of the one or more remote resources. For example, the compute node may be configured to monitor if one or more of the monitored resources were to exceed a threshold bandwidth or latency range as defined by the dynamic tolerated fragmentation. The compute node may be configured to determine that the monitored performance of the one or more remote resources is outside a threshold defined by the dynamic tolerated fragmentation.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: June 16, 2020
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Susanne M. Balle, Daniel Rivas Barragan, John Chun Kwok Leung, Suraj Prabhakaran, Murugasamy K. Nachimuthu, Slawomir Putyrski
  • Patent number: 10680976
    Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan, Alejandro Duran Gonzalez
  • Patent number: 10613999
    Abstract: Techniques and mechanisms for providing a shared memory which spans an interconnect fabric coupled between compute nodes. In an embodiment, a field-programmable gate array (FPGA) of a first compute node requests access to a memory resource of another compute node, where the memory resource is registered as part of the shared memory. In a response to the request, the first FPGA receives data from a fabric interface which couples the first compute node to an interconnect fabric. Circuitry of the first FPGA performs an operation, based on the data, independent of any requirement that the data first be stored to a shared memory location which is at the first compute node. In another embodiment, the fabric interface includes a cache agent to provide cache data and to provide cache coherency with one or more other compute nodes.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Thomas Willhalm, Karthik Kumar, Daniel Rivas Barragan, Patrick Lu
  • Patent number: 10547527
    Abstract: Apparatus, methods, and system for implementing cluster-wide operational metrics access for coordinated agile scheduling. One embodiment of the apparatus includes a memory to store instructions; a processing circuitry to execute instructions; and an interface circuitry. The interface circuitry to provide metrics associated with the apparatus to one or more subscriber nodes or network components in a managed cluster and to subscribe, via a metrics subscription request, to receive from one or more publisher nodes or network components in the managed cluster, metrics associated with the one or more publisher nodes or network components. The metrics to be stored in a dedicated location of the memory. The provision and subscription of metrics may be made using new protocols added to Layer 4 or transport layer of a network communication model and/or over a dedicated communication channel. The dedicated communication channel may be of low bandwidth with fixed priority and deterministic latency.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Raj K. Ramanujan, Gaspar Mora Porta, Daniel Rivas Barragan
  • Publication number: 20200004558
    Abstract: Examples may include techniques for collective operations in a distributed architecture. A collective operation request message from a computing node causes collective operations at one or more target computing nodes communicatively coupled with the computing node through a network switch. The collective operation request message also causes the network switch to perform collective operations on collective operation results received from the one or more target computing nodes.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 2, 2020
    Inventors: Francesc GUIM BERNAT, Kshitij A. DOSHI, Daniel RIVAS BARRAGAN, Alejandro DURAN GONZALEZ
  • Publication number: 20190220424
    Abstract: Techniques and mechanisms for providing a shared memory which spans an interconnect fabric coupled between compute nodes. In an embodiment, a field-programmable gate array (FPGA) of a first compute node requests access to a memory resource of another compute node, where the memory resource is registered as part of the shared memory. In a response to the request, the first FPGA receives data from a fabric interface which couples the first compute node to an interconnect fabric. Circuitry of the first FPGA performs an operation, based on the data, independent of any requirement that the data first be stored to a shared memory location which is at the first compute node. In another embodiment, the fabric interface includes a cache agent to provide cache data and to provide cache coherency with one or more other compute nodes.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Thomas Willhalm, Karthik Kumar, Daniel Rivas Barragan, Patrick Lu
  • Publication number: 20190124317
    Abstract: Apparatus, systems, methods, and articles of manufacture are disclosed for assigning a color to a point in three-dimensional (3D) video. An example system includes an aggregator to access data from real cameras, the data including spatial coordinates and colors for a plurality of two-dimensional (2D) points in video data captured by the real cameras. The aggregator is to create a point cloud correlating the 2D points to the 3D points. The example system also includes a selector to select a subset of the real cameras based on a position of a virtual camera. In addition, the example system includes an analyzer to: select a point from the point cloud in a field of view of the virtual camera; select one of the subset of real cameras having a non-occluded view of the point and a perspective closest to that of the virtual camera; and assign a color to the point based on color data associated with the selected one of the real cameras.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Daniel Rivas Perpen, Diego Prilusky
  • Patent number: 10255305
    Abstract: Technologies for object-based data consistency in a fabric architecture includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an object read request that includes an object identifier and a data consistency threshold from one of the computing nodes. The network switch is additionally configured to perform a lookup for a value of an object in the cache memory as a function of the object identifier and determine whether a condition of the value of the object violates the data consistency threshold in response to a determination that the lookup successfully returned the value of the object. The network switch is further configured to transmit the value of the object to the computing node in response to a determination that the condition of the value of the object does not violate the data consistency threshold. Other embodiments are described herein.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Thomas Willhalm, Karthik Kumar, Raj K. Ramanujan, Daniel Rivas Barragan
  • Publication number: 20190102224
    Abstract: Technologies for opportunistic acceleration overprovisioning for disaggregated architectures include a compute device. The compute device includes accelerator devices and a management logic unit. The management logic unit is to receive a plurality of job execution requests, each job execution request including a job requested to be accelerated received from an orchestrator server.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Francesc Guim Bernat, Suraj Prabhakaran, Daniel Rivas Barragan, Kshitij A. Doshi