Patents by Inventor Daniel Rivas

Daniel Rivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190095122
    Abstract: According to various aspects, a computing system may include one or more first memories of a first memory type and one or more second memories of a second memory type different from the first memory type and a memory controller. The memory controller may be configured to receive telemetry data associated with at least one of the one or more first memories and the one or more second memories, execute a data transfer between the one or more first memories and the one or more second memories in a first operation mode of the memory controller, suspend a data transfer between the one or more first memories and the one or more second memories in a second operation mode of the memory controller, and switch between the first operation mode and the second operation mode based on the telemetry data.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Francesc Guim Bernat, Kshitij Doshi, Daniel Rivas Barragan, Federico Ardanaz, Suraj Prabhakaran
  • Patent number: 10241885
    Abstract: In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a performance monitor circuit including a set of performance monitors to be programmably associated with a first kernel to execute on the FPGA; and a monitor circuit to receive kernel registration information of the first kernel from the processor and program a first set of performance monitors for association with the first kernel based on the kernel registration information. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Daniel Rivas Barragan, Patrick Lu
  • Publication number: 20190034340
    Abstract: An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 27, 2017
    Publication date: January 31, 2019
    Inventors: Kshitij A. Doshi, Francesc Guim Bernat, Daniel Rivas Barragan, Suraj Prabhakaran
  • Publication number: 20190004858
    Abstract: Technologies for dynamically sharing remote resources include a computing node that sends a resource request for remote resources to a remote computing node in response to a determination that additional resources are required by the computing node. The computing node configures a mapping of a local address space of the computing node to the remote resources of the remote computing node in response to sending the resource request. In response to generating an access to the local address, the computing node identifies the remote computing node based on the local address with the mapping of the local address space to the remote resources of the remote computing node and performs a resource access operation with the remote computing node over a network fabric. The remote computing node may be identified with system address decoders of a caching agent and a host fabric interface. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan, Alejandro Duran Gonzalez, Harald Servat
  • Publication number: 20190004862
    Abstract: Technologies for managing quality of service of a platform interconnect include a compute device. The compute device includes one or more processors, one or more resources capable of being utilized by the one or more processors, and a platform interconnect to facilitate communication of messages between the one or more processors and the one or more resources. The compute device is to obtain class of service data for one or more workloads to be executed by the compute device. The class of service data is indicative of a capacity of one or more of the resources to be utilized in the execution of each corresponding workload. The compute device is also to execute the one or more workloads and manage the amount of traffic transmitted through the platform interconnect for each corresponding workload as a function of the class of service data as the one or more workloads are executed.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Andrew J. Herdrich, Edwin Verplanke, Daniel Rivas Barragan
  • Publication number: 20190004910
    Abstract: A network controller, including: a processor; and a resource permission engine to: provision a composite node including a processor and a first disaggregated compute resource (DCR) remote from the processor, the first DCR to access a target resource; determine that the first DCR has failed; provision a second DCR for the composite node, the second DCR to access the target resource; and instruct the target resource to revoke a permission for the first DCR and grant the permission to the second DCR.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Daniel Rivas Barragan, Patrick Lu
  • Publication number: 20180351836
    Abstract: Particular embodiments described herein provide for a network element that can be configured to receive a request related to one or more disaggregated resources, link the one or more disaggregated resources to a local counter, receive performance related data from each of the one or more disaggregated resources, and store the performance related data in the local counter.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 6, 2018
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Daniel Rivas Barragan, Rahul Khanna
  • Publication number: 20180284993
    Abstract: Technology for a controller in a storage area network (SAN) node operable to perform data requests is described. The controller can receive a data request from a remote node. The data request can specify a data payload and a type of operation associated with the data request. The controller can select a kernel from a kernel table stored in the memory based on a set of rules. The kernel can be matched to the data request in accordance with the set of rules. The kernel can be configured using a bit stream. The controller can execute the kernel in order to perform the data request in accordance with the data payload and the type of operation.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan
  • Publication number: 20180285288
    Abstract: In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Daniel Rivas Barragan, Kshitij A. Doshi, Mark A. Schmisseur
  • Patent number: 10084724
    Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a computing node that includes a host fabric interface (HFI) usable to communicate with network computing devices of the fabric architecture. The HFI is configured to associate an object with a transaction identifier generated by the HFI for a corresponding transactional synchronization session managed by the HFI of the computing node. Additionally, the HFI is configured to store received data associated with received write transaction that include the transaction identifier in a local buffer of the HFI. Upon receiving a transactional synchronization session termination request, the HFI is configured to initiate a write of the data stored in the local buffer of the HFI to one of the one or more data storage devices of the computing node. Other embodiments are described herein.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan
  • Publication number: 20180267878
    Abstract: In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a performance monitor circuit including a set of performance monitors to be programmably associated with a first kernel to execute on the FPGA; and a monitor circuit to receive kernel registration information of the first kernel from the processor and program a first set of performance monitors for association with the first kernel based on the kernel registration information. Other embodiments are described and claimed.
    Type: Application
    Filed: March 16, 2017
    Publication date: September 20, 2018
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Daniel Rivas Barragan, Patrick Lu
  • Publication number: 20180239725
    Abstract: In an example, there is disclosed a computing apparatus, including: a host fabric interface (HFI) for communicatively coupling to a fabric controller of a fabric; an asynchronous data refresh (ADR) having an auxiliary power and an ADR buffer; and a memory controller including logic to: directly access a persistent fast memory of a remote computing device via the fabric; detect a primary power failure event; and flush data from the ADR buffer to the fabric controller.
    Type: Application
    Filed: February 17, 2017
    Publication date: August 23, 2018
    Applicant: Intel Corporation
    Inventors: Karthik Kumar, Suleyman Sair, Francesc Guim Bernat, Thomas Willhalm, Daniel Rivas Barragan
  • Publication number: 20180241802
    Abstract: Technologies for network switch based load balancing include a network switch. The network switch is to receive messages, route messages to destination computing devices, receive a request to perform a workload, and receive telemetry data from a plurality of server nodes in communication with the network switch. The telemetry data is indicative of a present load on one or more resources of each server node. The network switch is further to determine channel utilization data for each of the server nodes, select, as a function of the telemetry data and the channel utilization data, one or more of the server nodes to execute the workload, and assign the workload to the selected one or more server nodes. Other embodiments are also described and claimed.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Gaspar Mora Porta, Daniel Rivas Barragan
  • Publication number: 20180234486
    Abstract: A computing device, method and system to implement an adaptive compression scheme in a network fabric. The computing device may include a memory device and a fabric controller coupled to the memory device. The fabric controller may include processing circuitry having logic to communicate with a plurality of peer computing devices in the network fabric. The logic may be configured to implement the adaptive compression scheme to select, based on static information and on dynamic information relating to a peer computing device of the plurality of peer computing devices, a compression algorithm to compress a data payload destined for the peer computing device, and to compress the data payload based on the compression algorithm. The static information may include information on data payload decompression supported methods of the peer computing device, and the dynamic information may include information on link load at the peer computing device.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 16, 2018
    Applicant: Intel Corporation
    Inventors: Karthik Kumar, Francesc Guim Bernat, Thomas Willhalm, Nicolas A. Salhuana, Daniel Rivas Barragan
  • Patent number: 10049431
    Abstract: In an embodiment, a user equipment (UE) groups a plurality of images. The UE displays a first image among the plurality of images, determines an object of interest within the first image and a desired level of zoom, and determines to lock onto the object of interest in association with one or more transitions between the plurality of images. The UE determines to transition to a second image among the plurality of images, and detects, based on the lock determination, the object of interest within the second image. The UE displays the second image by zooming-in upon the object of interest at a level of zoom that corresponds to the desired level of zoom.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: August 14, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Bing Leng, Suzana Arellano, Daniel Rivas, Bing-Hsun Wu, Virginia Walker Keating
  • Patent number: 10038767
    Abstract: Technologies for using fabric supported sequencers in fabric architectures includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an sequencer access message from one of the plurality of computing nodes that includes an identifier of a sequencing counter corresponding to a sequencer session and one or more operation parameters. The network switch is additionally configured to perform an operation on a value associated with the identifier of the sequencing counter as a function of the one or more operation parameters, increment the identifier of the sequencing counter, and associate a result of the operation with the incremented identifier of the sequencing counter. The network switch is further configured to transmit an acknowledgment of successful access to the computing node that includes the result of the operation and the incremented identifier of the sequencing counter. Other embodiments are described herein.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Daniel Rivas Barragan
  • Publication number: 20180150343
    Abstract: Technologies for dynamically managing the reliability of disaggregated resources in a managed node include a resource manager server. The resource manager server includes communication circuit to receive resource data from a set of disaggregated resources that indicates reliability of each disaggregated resource of the set of disaggregated resources and a node request to compose a managed node. The resource manager server further includes a compute engine to determine node parameters from the node request indicative of a target reliability of one or more disaggregated resources of the set of disaggregated resources to be included in the managed node, compose a managed node from the set of disaggregated resources that satisfies the node parameters by configuring the compute sled to utilize the disaggregated resources of the managed node for the execution of a workload, and monitor the disaggregated resources of the managed node for a failure.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 31, 2018
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Murugasamy K. Nachimuthu, Daniel Rivas Barragan
  • Publication number: 20180097743
    Abstract: Apparatus, methods, and system for implementing cluster-wide operational metrics access for coordinated agile scheduling. One embodiment of the apparatus includes a memory to store instructions; a processing circuitry to execute instructions; and an interface circuitry. The interface circuitry to provide metrics associated with the apparatus to one or more subscriber nodes or network components in a managed cluster and to subscribe, via a metrics subscription request, to receive from one or more publisher nodes or network components in the managed cluster, metrics associated with the one or more publisher nodes or network components. The metrics to be stored in a dedicated location of the memory. The provision and subscription of metrics may be made using new protocols added to Layer 4 or transport layer of a network communication model and/or over a dedicated communication channel. The dedicated communication channel may be of low bandwidth with fixed priority and deterministic latency.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Raj K. Ramanujan, Gaspar Mora Porta, Daniel Rivas Barragan
  • Publication number: 20180095906
    Abstract: Apparatuses, systems, and methods for coherently sharing data across a multi-node network is described. A coherency protocol for such data sharing can include identifying a memory access request from a requesting node for an I/O block of data in a shared I/O address space of a multi-node network, determining a logical ID and a logical offset of the I/O block, identifying an owner of the I/O block, negotiating permissions with the owner of the I/O block, and performing the memory access request on the I/O block.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Kshitij A. Doshi, Francesc Guim Bernat, Daniel Rivas Barragan
  • Publication number: 20180089248
    Abstract: Fabric supported replication enables hardware replication and hardware-assisted software replication of objects on behalf of replication software. Software specifies to a communication fabric of a storage system which objects to replicate and where and how to replicate them. A storage protocol defines which storage operations modify replicated objects. Alternatively, nodes in the communication fabric infer whether storage operations modify replicated objects. Either way, the fabric logic automatically propagates replicated objects and updates to replicated objects to replica nodes based on the software specification. The fabric logic initiates message flows between the replica nodes in order to perform the hardware replication and hardware-assisted software replication.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Francesc GUIM BERNAT, Daniel A. RIVAS BARRAGAN, Kshitij A. DOSHI, Mark A. SCHMISSEUR, Steen LARSEN