Abstract: The present disclosure generally relates to the fabrication of and methods for creating a reversible tri-state memory device which provides both forward and reverse write and read drive to a bi-directional RRAM cell, thus allowing writing in the forward and reverse directions. The memory device, however, utilizes a single transistor “on pitch” which fits between two metal lines traversing the array tile.

Abstract: The present disclosure generally relates to the fabrication of and methods for creating a reversible tri-state memory device which provides both forward and reverse write and read drive to a bi-directional RRAM cell, thus allowing writing in the forward and reverse directions. The memory device, however, utilizes a single transistor “on pitch” which fits between two metal lines traversing the array tile.

Abstract: The present disclosure generally relates to non-volatile memory arrays and memory devices in which a leakage current through an OTS is utilized to pre-charge a circuit of a memory chip. By running an additional wire on each side of a tile which is orthogonal to, above, or below the X and Y select wires, a high value resistance material, such as an OTS, may be deposited at the intersection. The OTS allows the word line or bit line to be selected without pulling excessive leakage to the select wire from the bias voltage, such as V/2. A thickness of the OTS is adjusted such that the Vt of the OTS is greater than V/2, with margin, and the OTS does not turn on when the OTS is selected. A resistance is created between the V/2 wire and the word line select wire or the bit line select wire.

Abstract: A 3D cross-point memory array includes a bitline and a word line. Both the bitline and the word line have multiple selector switches. Each switch of a corresponding bitline or word line is connected to a horizontal conductor or a vertical conductor so that a given bitline or word line has two switches, a horizontal conductor and a vertical conductor. By activating a particular horizontal conductor and vertical conductor, a specific bitline or word line is selected.

Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.

Abstract: The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4F2 3D cross-point memory array has been formed.

Abstract: The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4 F2 3D cross-point memory array has been formed.

Abstract: The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4F2 3D cross-point memory array has been formed.

Abstract: A 3D cross-point memory array includes a bitline and a word line. Both the bitline and the word line have multiple selector switches. Each switch of a corresponding bitline or word line is connected to a horizontal conductor or a vertical conductor so that a given bitline or word line has two switches, a horizontal conductor and a vertical conductor. By activating a particular horizontal conductor and vertical conductor, a specific bitline or word line is selected.

Abstract: The present invention relates to systems for guiding a vehicle to a trailer that can easily be installed or removed, and in particular relates to systems for guiding a vehicle to a trailer to facilitate coupling the vehicle and trailer together. The present invention is a means and a method for continuously determining the heading and/or distance to the trailer to assist a driver to couple a vehicle and trailer together. A device containing an inertial measurement unit is manually positioned proximate to the hitch ball of the vehicle and then positioned proximate to the coupler of the trailer and the motion is tracked and stored to enable the desired path between the two positions to be plotted. This path is then used to guide the driver in bringing the hitch ball and coupler together.

Abstract: The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.

Abstract: The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.

Abstract: The present disclosure generally relates to the fabrication of metal-oxide-semiconductor (MOS) select transistors in a vertical orientation such that the transistor pair fits within the footprint of a 4F2 memory cell. The present disclosure further relates to the simultaneous fabrication of a vertical stack of transistors in which each transistor is distinct, as opposed to being serially connected in a NAND-like string. An initial stack of materials is built to include silicon layers to act as source and drain regions as well as to serve as epitaxial growth seed points. As such, the transistor disclosed may be utilized in conjunction with memory elements such as Phase Change, Resistive, or Magnetic RAM memory within array designs, among others.

Abstract: The present invention is a guidance computing system used by the driver of a vehicle towing a trailer while backing-up that rapidly calculates and predicts the direction in which the tow vehicle and trailer will become generally in-line for a given position of the steering wheel, thereby enabling the use of slower, lower cost microcomputers. This is accomplished by using a predetermined table, based on a baseline trailer of known length, having a measure of turning as one of its axes; such an axis is necessary to facilitate ratiometric scaling to convert table values to correspond to any length trailer. In a specially equipped vehicle incorporating servomechanisms to enable the vehicle to steer itself, the driver indicates the direction desired for the trailer to travel. The present invention also predicts left and right path limits for controlling the direction of the trailer when maneuvering complex paths.

Abstract: The present disclosure generally relates to a memory cell and methods for generating a pulse within the memory cell. As such, a geometric arrangement of transistors is disclosed that allows the transistor pulse signal generator circuit to precharge both sides of the memory cell and, subsequently, bring opposite sides of the memory cell quickly to different voltages. The circuit and wiring fabrication provided, when combined with a related transistor manufacturing process, yields pulse generating logic at the memory cell to enable the formation of a well-defined pulse while fitting within the 4F2 footprint of the memory cell. As such, the speed and pulse shape requirements of PCM, MRAM, other such cross-point memory technologies, sensor arrays, and/or pixel displays may take advantage of the reduced RC circuitry delays.

Abstract: The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.

Abstract: The present invention is a guidance computing system used by the driver of a vehicle towing a trailer while backing-up that rapidly calculates and predicts the direction in which the tow vehicle and trailer will become generally in-line for a given position of the steering wheel, thereby enabling the use of slower, lower cost microcomputers. This is accomplished by using a predetermined table, based on a baseline trailer of known length, having a measure of turning as one of its axes; such an axis is necessary to facilitate ratiometric scaling to convert table values to correspond to any length trailer. In a specially equipped vehicle incorporating servomechanisms to enable the vehicle to steer itself, the driver indicates the direction desired for the trailer to travel. The present invention also predicts left and right path limits for controlling the direction of the trailer when maneuvering complex paths.

Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.

Abstract: The present invention is a hitch angle sensor that utilizes an inertial measurement unit (IMU) in the vehicle and an IMU in the trailer. The present invention measures the rotation of the vehicle and the trailer to determine the change in the angle between the vehicle and the trailer.

Abstract: The present invention relates to display means for systems for guiding a trailer while backing, and in particular to graphical display means to provide information to an operator who is steering, and controlling the accelerator and breaks by suggesting the amount of steering to apply to the towing vehicle to cause the trailer to be directed to where the operator wants the trailer to go.