Abstract: The present invention is a method for accessing more than one block of correctable information at a time when it is most efficient to access more bits of information at a time on a given dimension, for example from a multiple bit per cell (MLC) memory element, than the error correction algorithm can correct. Since it may be more efficient to access more bits of information at a time on a given dimension than the error correction algorithm can correct, that access is performed in this most efficient way, but the information is divided into correctable blocks within this information such that the error correction algorithm can still compensate for a serious fault along a given dimension. Furthermore, the present invention can be employed even when the number of bits retrieved along a given dimension is less than the number of correctable bits when it is desired to protect against a given number of faults which could, in total, exceed the number of correctable bits.

Abstract: A random access memory device is disclosed having an interface that is compatible with a NAND FLASH memory device such that the device can be operated with a standard NAND memory device's controller device. This memory device is can store data internally using any random access storage technology including PRAM, MRAM, RRAM, FRAM, OTP-RAM and 3-D memory.

Abstract: Solid-state memory devices featuring pluralities of lines of data storage elements are configured for read and/or write access by alternately or simultaneously accessing different lines.

Abstract: A memory-array is disclosed in which an array of non-linear conductors such as diodes is constructed having an area per memory cell of 4F2 and comprises a plurality of conductors fabricated as doped semiconductor conducting lines in the substrate such that, during normal operation, an unselected conductor has a zero bias to the substrate and a selected conductor has a reverse bias to the substrate for minimizing current leakage

Abstract: A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Abstract: A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits whereby these address bits are transformed by transforming logic. This transforming logic may include adders. Transforming logic may alternately include comparators or exclusive-or circuits. Transforming logic comprising adders may include overflow carry bits that are discarded, ignored, or otherwise not used or the overflow logic may be omitted altogether.

Abstract: The present invention relates to corded electric devices and more particularly to corded electric devices that move their location such as an electric lawn mower. The present invention is a device for handling the electric cord of a device such as an electric lawn mower or some other movable platform to which electric power is provided (a lawn mower is a movable platform having a device for cutting grass such as spinning blades). The present invention manages the position of a cord as the platform on which it is mounted is moved.

Abstract: The present invention helps a driver steer a vehicle while backing up a trailer. A trailer being pushed wants to turn around and be pulled (i.e., to jackknife). To compensate for this instability, the driver must skillfully control his steering to cause the trailer to alternately move to be pulled from the opposite side thereby repeatedly crossing the centerline of the pushing vehicle. The moment when the trailer crosses this centerline is the moment of greatest instability and the position in which the driver would most desire to have the trailer travel. A pointer indicates in what direction the trailer is presently being directed; to backup the trailer, the driver turns the vehicle's wheel such that the pointer is kept pointing in the direction of the intended trailer destination. The present invention can be adapted to most vehicle and trailer combinations with minimal cost and complexity.

Abstract: The present invention is a method of applying a topographical surface to a part such as a substrate without the need for low temperature softening of that part while retaining high aspect ratios and densely packed features in that topography. A substrate, selected for its ability to be processed at a given desired temperature, has a layer of material applied to its surface. This layer is selected, among other reasons, for its ability to be molded. Typically, it is expected that the substrate will be able to withstand the higher temperatures of semiconductor post-processing whereas the applied layer will be moldable at low temperatures. This combination enables low cost embossing of a topography into this surface layer. The present invention comprises means to transfer this topography from the low temperature material into the higher temperature substrate.

Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Abstract: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device.

Abstract: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device.

Abstract: As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory manufacturing costs are significant and will grow as the capacity of the devices grows—the higher the memory's capacity, the more storage locations that must be tested, and the longer the testing operation will take. The cost of the testing can be calculated by dividing the amortized cost of the test equipment by the number of devices tested. As memory devices enter the Gigabyte range and larger, the number of devices that can be tested by a given piece of test equipment will go down. As a result, the cost per unit attributable to testing will rise.

Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Abstract: The present invention, when used in conjunction with a trailer to be backed-up, will indicate to the driver which direction to steer his vehicle as well as when and how much to steer. Trailers have been around for many years, yet every summer and winter one can observe the owners of boats and snowmobiles, respectively, backing up those devices on trailers with great difficulty. The problem arises from the fact that a trailer being backed-up is an inherently unstable system. A trailer being pushed wants to turn around and be pulled (i.e., to jackknife) instead. To compensate for this instability, the driver must skillfully reverse the direction of his steering so as to cause the trailer to want to turn around and be pulled from the opposite side thereby repeatedly crossing the centerline of the pushing vehicle. The moment when the trailer crosses this centerline is the moment of greatest instability and the position in which the driver would most desire to have the trailer travel.

Abstract: As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory manufacturing costs are significant and will grow as the capacity of the devices grows—the higher the memory's capacity, the more storage locations that must be tested, and the longer the testing operation will take. The cost of the testing can be calculated by dividing the amortized cost of the test equipment by the number of devices tested. As memory devices enter the Gigabyte range and larger, the number of devices that can be tested by a given piece of test equipment will go down. As a result, the cost per unit attributable to testing will rise.

Abstract: The present invention is a means for constructing a high density memory device for very low cost by fabricating the device three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers—not the exponentially greater number of decoded rows and columns. Furthermore, to keep the testing of the device low in cost, a row and column interconnect means is disclosed for testing the any two-dimensional array within the three-dimensional array with a single continuity and short-circuit test.

Abstract: As advances continue to be made in the area of high density data storage devices, the storage of such data as music (as is presently stored on audio CD-ROM's), books on tape, videos, movies and the like will become more common. However, when this type of information is stored digitally, the risk of data piracy will increase. What is needed is an integrated copy deterring mechanism for stored digitized information such as audio recordings and the like. The present invention is a digital data storage device which comprises one or more Digital to Analog Converters (DAC's). By incorporating Digital to Analog Converters on the chip or within the chip's packaging (a hybrid device), data being output could be made available in an analog form only (although some portion of the stored information could still be made available in a digital format). A device employing the analog output means disclosed could comprise read only data storage means or writable or one time programmable data storage means.