Abstract: Disclosed herein are apparatuses and methods for treating neurological disorders by electro-stimulation. The apparatus (10) for treating neurological disorders includes at least one electrode (12) implantable in the brain of a patient, and a processing and stimulation device (14) connected to the at least one electrode (12). The processing and stimulation device (14) may include a stimulation module (16) configured to generate a stimulation signal to be sent to the at least one electrode (12), and an acquisition module (20) that measures cerebral activity coming from the brain of the patient. The acquisition module (20) may have a front-end block (27) configured to amplify the potential difference of its input signals (V1a, V2a) and to filter a stimulus artifact and may include a multi-stage fully-differential switched capacitor circuit (e.g., an integrated circuit) configured for discrete-time signal processing.

Abstract: The present disclosure relates to apparatuses and methods for treating neurological disorders by electro-stimulation. In some embodiments, the apparatus includes a stimulation module configured to generate a stimulation signal to be sent to at least one implantable electrode, and an acquisition module configured to acquire a signal measured by the at least one implantable electrode from a patient. The acquisition module may include a front-end block configured to amplify a potential difference of input signals (V1a, V2a) received by the acquisition module and to filter a stimulus artifact by cutting off frequencies above a predefined frequency band. The front-end block may include a multi-stage fully-differential switched capacitor circuit configured for discrete-time signal processing.

Abstract: Disclosed herein are apparatuses and methods for treating neurological disorders by electro-stimulation. The apparatus (10) for treating neurological disorders includes at least one electrode (12) implantable in the brain of a patient, and a processing and stimulation device (14) connected to the at least one electrode (12). The processing and stimulation device (14) may include a stimulation module (16) configured to generate a stimulation signal to be sent to the at least one electrode (12), and an acquisition module (20) that measures cerebral activity coming from the brain of the patient. The acquisition module (20) may have a front-end block (27) configured to amplify the potential difference of its input signals (V1a, V2a) and to filter a stimulus artifact and may include a multi-stage fully-differential switched capacitor circuit (e.g., an integrated circuit) configured for discrete-time signal processing.

Abstract: Disclosed herein are apparatuses and methods for treating neurological disorders by electro-stimulation. The apparatus for treating neurological disorders includes at least one electrode implantable in the brain of a patient, and a processing and stimulation device connected to the at least one electrode. The processing and stimulation device may include a stimulation module configured to generate a stimulation signal to be sent to the at least one electrode, and an acquisition module that measures cerebral activity coming from the brain of the patient. The acquisition module may have a front-end block configured to amplify the potential difference of its input signals (V1a, V2a) and to filter a stimulus artifact and may include a multi-stage fully-differential switched capacitor circuit (e.g., an integrated circuit) configured for discrete-time signal processing.

Abstract: Disclosed herein are apparatuses and methods for treating neurological disorders by electro-stimulation. The apparatus (10) for treating neurological disorders includes at least one electrode (12) implantable in the brain of a patient, and a processing and stimulation device (14) connected to the at least one electrode (12). The processing and stimulation device (14) may include a stimulation module (16) configured to generate a stimulation signal to be sent to the at least one electrode (12), and an acquisition module (20) that measures cerebral activity coming from the brain of the patient. The acquisition module (20) may have a front-end block (27) configured to amplify the potential difference of its input signals (V1a,V2a) and to filter a stimulus artifact and may include a multi-stage fully-differential switched capacitor circuit (e.g., an integrated circuit) configured for discrete-time signal processing.

Abstract: A highly selective frequency filter is created from lossy components such as found in standard integrated circuit technologies, including particularly CMOS technologies, without the use of active loss cancellation circuitry. The filter configuration is based on using inductively coupled planar inductors for introducing a mutual inductance factor that advantageously alters the frequency response of the filter.

Abstract: An analog input signal that is sampled at a predetermined rate is multiplied by a corresponding binary code sequence, i.e. “+1” or “−1” by the multiplier. The output of this multiplier is applied in conjunction with a signal supplied by the negative feed back circuit to the analog integrator. The quantization circuit quantizes the output signal of the analog integrator into N levels and outputs a digital word. This digital word is delayed by a unit time interval by a digital delay circuit and then processed by the above mentioned negative feed back circuit. As a result of this signal magnitude reducing process, the required integrating capacitance can be minimized without risks of saturation effects. Additionally, the output is already in digital form as required by the subsequent system blocks.

Abstract: An analog input signal that is sampled at a predetermined rate is multiplied by a corresponding binary code sequence, i.e. “+1” or “−1” by the multiplier. The output of this multiplier is applied in conjunction with a signal supplied by the negative feedback circuit to the analog integrator. The quantization circuit quantizes the output signal of the analog integrator into N levels and outputs a digital word. This digital word is delayed by a unit time interval by a digital delay circuit and then processed by the above mentioned negative feedback circuit. As a result of this signal magnitude reducing process, the required integrating capacitance can be minimized without risks of saturation effects. Additionally, the output is already in digital form as required by the subsequent system blocks.

Abstract: The circuit of a two-stage fully differential amplifier includes a differential input stage, two output stages and a common mode feedback circuit coupled to the output nodes of the amplifier. The amplifier also includes a non-inverting stage coupled to a respective output node of the differential input stage for driving the respective output stage. Each auxiliary non-inverting stage of the two branches of the fully differential amplifier uses as a biasing current generator, the load device of the branch of the differential input stage to the output of which the non-inverting stage is coupled. The fully differential amplifier permits the use of a null-consumption common mode feedback circuit as normally employed only in a single stage fully differential amplifier.

Abstract: The circuit includes a filter to which an analog signal is applied, a quantizer driven by the filter, a sampler at a desired frequency driven by the quantizer and a PCM encoder driven by the sampler. The quantizer generates a quantize signal according to the received analog signal and further generates a difference signal according to the difference between a quantized signal and the analog signal. A feedback circuit feeds back the difference signal from the quantizer to a stage of the filter so that the overall transfer function from the input of the feedback circuit to the output of the filter is equivalent to a low pass filtering.

Abstract: An improved MOS capacitor array formed on a semiconductor substrate comprises rectangular strips of an active region overlapped by rectangular strips of conductive material. The active region and conductive material are separated by an insulating layer. The strips form an array of capacitors which are more tightly packed than the prior art and which are less sensitive to alignment errors than the prior art.

Abstract: A multichannel ADC is fabricated on a single IC with each analog channel for concurrently processing input analogue signal in a pipelined manner and including a dual purpose intermediate amplifier for amplifying an input voltage to be converted and providing a reference voltage for use during conversion. A unique capacitor array reduces the area required to implement the convertors.

Abstract: A method of reconstructing an analog signal, particularly for digital telephony, comprises a first step of digital-to-analog conversion, wherein a first reconstruction of the analog signal is provided by introducing a distortion component into the frequency spectrum whose amplitude decreases with the signal frequency, and a second step of filtering carried out by means of a reconstruction filter provided with integrators and having a cut-off frequency F.sub.t. That attenuating distortion component is utilized instead of one of the integrators in the reconstruction filter, to afford a reduction of the overall design of the circuit device operating in accordance with this method, and bring about, as a result, decreased occupation of the integrated circuit and power dissipation.

Abstract: A fully differential sigma-delta signal processor for use in high-speed voiceband or higher-frequency applications. The processor receives the two polarities of a differential input signal and passes them to a differential-amplifier integrator through a switched sampling capacitor arrangement. The capacitors are each alternately and concurrently switched back and forth between the two signal paths for the two polarities of the input signal responsive to a clock signal in such a manner as to sample and integrate the input signal at an effective signal transfer rate of at least twice the clock frequency. An analog-to-digital converter defines a digital feedback-control signal characteristic of the integrator output signal. A second switched-capacitor arrangement selectively applies a feedback signal to the integrator inputs, responsive to the digital control signal, at a switching rate comparable to the effective signal transfer rate through the integrator.

Abstract: The filter comprises four operational amplifiers in cascade, with switched capacitors in series at the input of every amplifier, with fixed capacitors in parallel to two of said amplifiers, with fixed and switched capacitors in parallel to the remaining amplifiers, and with fixed and switched capacitors in common to groups of several amplifiers in cascade. According to the invention, a path of fixed and switched capacitors in parallel connects the input of the filter to the input of the fourth amplifier, and a fixed capacitor connects the input of the filter to the input of the second amplifier.

Abstract: The sampled-data band-pass filter device is based on the phenomemon of aliasing, and allows the substantially unattenuated passage of the components of an input signal at a frequency included within an interval comprised between a first frequency (f.sub.sL) and a second frequency (f.sub.sH), arranged around a third frequency (f.sub.sO), while it substantially attenuates the components of the input signal at frequencies outside said interval, and furthermore automatically performs the shift to low-frequency, around a fourth frequency (f.sub.O), of the components of the input signal which have passed without attenuation. According to the invention, the device comprises, as filter element, a sampled-data band-pass filter which employs, as sampling frequency, a fifth frequency (f.sub.s) equal to a whole submultiple of a sixth frequency (nf.sub.s) equal to the sum of the third frequency (f.sub.sO) and the fourth frequency (f.sub.

Abstract: A CMOS power operational amplifier with large output voltage swing and high noise rejection is obtained by coupling a folded cascode type differential input stage and an output stage comprising an intermediate signal shifting amplifier and two common source output stages. Constant current generators inject into the drain of grounded gate MOS transistors pairs of said folded cascode type stage and of said intermediate signal shifting amplifier, respectively, a current which is pulled out of the source of the same grounded gate transistors by other constant current generators for increasing the effective transconductance of said grounded gate transistors pairs.

Abstract: In a Pulse Code Modulated (PCM) circuit chip, apparatus in the transmit path to compensate for an offset voltage signal from a band-pass filter includes an up-down counter which is actuated to provide a digital value equivalent to the offset signal and a digital to analog converter coupled to the counter to provide an analog signal representing the digital value in the counter. During an initialization phase, the counter is incremented until the digital value of the counter provides, by means of the digital to analog converter, an analog signal that compensates for the off-set signal. After the initialization phase when the band-pass filter's offset voltage is compensated, then other circuitry including an exclusive OR gate and an associated overflow counter are used to eneable or disable the up-down counter to insure that the PCM output signal is an accurate representation of the analog input signal.

Abstract: A charge redistribution analog-to-digital converter is described that permits their ncorporation of offset voltage correction to provide an accurate reflection in the digitalized output signal of the analog input signal. In a distributed capacitor successive approximation device, additional capacitors are added both to a most significant bit array group of capacitors and to a least significant array group of capacitors that are used in conjunction with the offset voltage. The value of the offset voltage is stored in a register and the register determines various switch positions that determine the value of the offset voltage incorporated in the final output voltage.

Abstract: A fully differential, CMOS, operational power amplifier, particularly useful as output buffer in monolithic analog subsystems, includes an input differential stage, two gain stages and two output stages. Each output stage may be individually provided with a functional feedback loop and locally compensated for reestablishing sufficient stability. An output common mode control circuit, operable in a continuous or sampled manner, is also contemplated, as well as a special circuit for controlling the DC biasing current through the output stages under rest conditions. The amplifier may be used indifferently as a balanced (differential) output or as a single-ended output amplifier without any depression of its performances.