Abstract: A method for forming viable floating gate memory cells in a semiconductor substrate. At various points within the memory cell manufacturing process rapid thermal annealing is used to repair any damage that may be caused to the crystals in the substrate by various processing steps. By quickly repairing any damage to the crystals of the substrate, the rate and amount of overall transient enhanced diffusion of the various dopants within the substrate can be greatly reduced, thereby allowing the production of a viable memory cell. Specifically, the present invention uses rapid thermal annealing during and following the formation of the source and drain regions and the interconnection regions effecting electrical connection between the source regions. This desensitizes the erase rates of the semiconductor device to the etching conditions employed to form the connections.

Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

Abstract: The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

Abstract: A method of erasing a flash memory cell to suppress bi-directional tunnel oxide stress that includes applying a negative voltage to the control gate of the flash memory cell, applying a bias voltage to the substrate of the flash memory cell and applying a bias voltage to the drain of the flash memory cell that equals the bias voltage applied to the substrate minus a fraction of a diode voltage drop across the drain junction formed between the drain and the substrate. The bias voltage applied to the drain is selected so that the drain junction is not forward biased. The fraction is in the range of 20% to 80% of the diode voltage drop.

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack.

Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.