Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.

Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract: One method disclosed includes, among other things, forming an uncut line-type gate structure above first and second spaced-apart active regions of a semiconductor substrate, forming a sidewall spacer around a perimeter of the line-type gate structure, performing at least one etching process to remove an axial portion of a gate cap layer and an axial portion of a gate electrode that are positioned above the isolation region so as to thereby define first and second cut end surfaces of first and second gate electrodes, respectively, and an isolation plug cavity and forming a gate cut isolation plug in the isolation plug cavity.

Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.

Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.

Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

Abstract: One method herein includes forming a plurality of spaced-apart trenches that extend at least partially into a semiconducting substrate, wherein the trenches define a fin structure comprised of first and second layers of semiconducting material, wherein the first layer of semiconducting material is selectively etchable relative to the substrate and the second layer of semiconducting material, forming a sacrificial gate structure above the fin, wherein the gate structure includes a gate insulation layer and a gate electrode, forming a sidewall spacer adjacent the gate structure, performing an etching process to remove the sacrificial gate structure, thereby defining a gate cavity, performing at least one selective etching process to selectively remove the first layer of semiconducting material relative to the second layer of semiconducting material within the gate cavity, thereby defining a space between the second semiconducting material and the substrate, and forming a final gate structure in the gate cavity.

Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.

Abstract: Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.

Abstract: Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon.

Abstract: Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure.

Abstract: Disclosed herein are various methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom. In one example, the method includes forming a layer of silicon dioxide above a structure, converting at least a portion of the layer of silicon dioxide into a silicon-salt layer and converting at least a portion of the silicon-salt layer to a layer of silicon.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Abstract: A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device.

Abstract: A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device.

Abstract: A method for forming a polysilicon FinFET (10) or other thin film transistor structure includes forming an insulative layer (12) over a semiconductor substrate (14). An amorphous silicon layer (32) forms over the insulative layer (12). A silicon germanium seed layer (44) forms in association with the amorphous silicon layer (32) for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (32). During the annealing step, silicon germanium seed layer (44), together with silicon germanium layer (34), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (16), drain (18), and channel (20) regions are formed within the polysilicon layer. A double-gated region (24) forms in association with source (16), drain (18), and channel (20) to produce polysilicon FinFET (10).