Patents by Inventor Daniel Weber

Daniel Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
    Patent number: 7761724
    Abstract: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: July 20, 2010
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
    Patent number: 7730338
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: June 1, 2010
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
    Patent number: 7724589
    Abstract: A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: May 25, 2010
    Assignee: Google Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Event Detection/Anomaly Correlation Heuristics
    Publication number: 20100115617
    Abstract: A system for detecting network intrusions and other conditions in a network is described. The system includes a plurality of collector devices that are disposed to collect data and statistical information on packets that are sent between nodes on a network. An aggregator device is disposed to receive data and statistical information from the plurality of collector devices. The aggregator device produces a connection table that maps each node on the network to a record that stores information about traffic to or from the node. The aggregator runs processes that determine network events from aggregating of anomalies into network events.
    Type: Application
    Filed: April 19, 2008
    Publication date: May 6, 2010
    Inventors: Daniel Weber, Prem Gopalan, Massimiliano Antonio Poletto
  • SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT
    Publication number: 20090285031
    Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.
    Type: Application
    Filed: July 22, 2009
    Publication date: November 19, 2009
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Biomechanically advantageous patient transfer device
    Patent number: 7614102
    Abstract: In one embodiment, the present invention is a biomechanically advantageous patient transfer device. One embodiment of a patient transfer device includes a body configured for supporting a patient thereon, a plurality of flanges coupled to the body and extending outward therefrom, and a plurality of handles configured for allowing the patient transfer device to be lifted, at least one handle being formed in each flange.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: November 10, 2009
    Assignee: LaProxima Technologies, Inc.
    Inventors: Donald G. Helt, III, Daniel Weber, Peter M. Sanzio
  • System and method for simulating an aspect of a memory circuit
    Patent number: 7609567
    Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: October 27, 2009
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • System and method for power management in memory systems
    Patent number: 7590796
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: September 15, 2009
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Power saving system and method for use with a plurality of memory circuits
    Patent number: 7580312
    Abstract: A power saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accessed. In response to the identification of the at least one memory circuit, a power saving operation is initiated in association with the at least one memory circuit.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: August 25, 2009
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Interface circuit system and method for performing power saving operations during a command-related latency
    Patent number: 7581127
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: August 25, 2009
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY CIRCUIT SYSTEM AND METHOD
    Publication number: 20090024790
    Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
    Type: Application
    Filed: October 30, 2007
    Publication date: January 22, 2009
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY CIRCUIT SYSTEM AND METHOD
    Publication number: 20090024789
    Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
    Type: Application
    Filed: October 30, 2007
    Publication date: January 22, 2009
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Interface circuit system and method for performing power management operations utilizing power management signals
    Patent number: 7472220
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: December 30, 2008
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • BIOMECHANICALLY ADVANTAGEOUS PATIENT TRANSFER DEVICE
    Publication number: 20080295250
    Abstract: In one embodiment, the present invention is a biomechanically advantageous patient transfer device. One embodiment of a patient transfer device includes a body configured for supporting a patient thereon, a plurality of flanges coupled to the body and extending outward therefrom, and a plurality of handles configured for allowing the patient transfer device to be lifted, at least one handle being formed in each flange.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 4, 2008
    Inventors: DONALD G. HELT, III, Daniel Weber, Peter M. Sanzio
  • NEUROMUSCULAR THERAPEUTIC DEVICE
    Publication number: 20080300519
    Abstract: Apparatus and method for delivering audible, electrical or mechanical tones having a specific characteristic to a human vestibular system to achieve thereby a therapeutic result.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 4, 2008
    Inventors: Donald G. Helt, III, Daniel Weber, Peter M. Sanzio
  • Detection of unauthorized access in a network
    Patent number: 7461404
    Abstract: A system for detecting network intrusions and other conditions in a network is described. The system includes a plurality of collector devices that are disposed to collect data and statistical information on packets that are sent between nodes on a network. An aggregator device is disposed to receive data and statistical information from the plurality of collector devices. The aggregator device produces a connection table that maps each node on the network to a record that stores information about traffic to or from the node. The aggregator runs processes that determine network events from aggregating of anomalies into network events.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: December 2, 2008
    Assignee: Mazu Networks, Inc.
    Inventors: Anne Elizabeth Dudfield, Massimiliano Antonio Poletto, Daniel Weber
  • INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS
    Publication number: 20080239858
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.
    Type: Application
    Filed: April 29, 2008
    Publication date: October 2, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT
    Publication number: 20080239857
    Abstract: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system.
    Type: Application
    Filed: April 29, 2008
    Publication date: October 2, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Reservoir Simulation
    Publication number: 20080167849
    Abstract: Disclosed are methods for simulating pressures and saturations of oil, gas, and water in an oil reservoir with production and injection wells, which include (1) using of new approximating linear algebraic (finite difference) equations that more accurately represent actual pressures by basing the equations on new functional forms: ln(r) or 1/r, (2) solve the set equations using by defining a coarse grid array and a fine grid array nested in the fine grid array, and solving the coarse grid array and using the resulting solution to fix points in the fine grid array before it is solved, and (3) defining and solving a dynamic grid array based upon constant saturation contours.
    Type: Application
    Filed: June 4, 2005
    Publication date: July 10, 2008
    Applicant: BRIGHAM YOUNG UNIVERSITY
    Inventors: Hugh Hales, Daniel Weber, Ben Hardy, Brad Bundy, Larry Baxter
  • Handheld scanning device
    Patent number: D609706
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: February 9, 2010
    Assignee: LaProxima Technologies, Inc.
    Inventors: Donald G. Helt, III, Peter M. Sanzio, Daniel Weber