Abstract: A system and method are provided, wherein a first component and a second component are operable to interface a plurality of memory circuits and a system.

Abstract: A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.

Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.

Abstract: A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface.

Abstract: A system and method are provided including an interface circuit in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the plurality of memory circuits and the system for simulating at leas one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The interface circuit is further operable to control refreshing of the plurality of memory circuits.

Abstract: A system and method are provided. In response to the receipt of a refresh control signal, a plurality of refresh control signals is sent to the memory circuits at different times.

Abstract: A system and method are provided including a component in communication with a plurality of memory circuits and a system. The component is operable to interface the memory circuits an the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The component is further operable to perform a power saving operation.

Abstract: A system and method are provided for simulating a different number of memory circuits. Included is an interface circuit in communication with a first number of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number. Further, the interface circuit interfaces a majority of address or control signals of the memory circuits.

Abstract: A data input system has a key pad with a plurality of keys and a display. The selected key is displayed in the display, but the character size of the selected key on the display is small and difficult to recognize. The face of the selected key appears on the display as a pop-up display in an enlarged scale. Thus, it is easy to recognize the selected key.

Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits.

Abstract: In an antenna communications unit which, when installed on trucks, allows two-way communications between a driver and fleet logistic centers, historically, a global positioning system (GPS) antenna within a radome has been housed in a cavity beneath a transceiver's messaging antenna. A method and device is provided which moves the GPS antenna from beneath the messaging antenna and places it in an enclosure mounted to the radome.

Abstract: A system for sensing velocity of a wheeled vehicle has a flexible arm connected to a speed sensor and wireless transmitter at one end and to an adjustable strap or clamp at the other end. The strap is attached near the wheel to be measured. The sensor can then be positioned via the flexible arm to a location immediately adjacent the wheel. There is also a display unit connected to another strap or clamp. The display unit contains a wireless receiver that receives the data transmitted by the transmitter on the sensor, and a microprocessor that calculates the data and displays it for the user to view. A magnetic strip is attached directly to one of the wheels of the device. As the wheel rotates, the magnetic strip passes by the sensor positioned adjacent the wheel, and this passage is recorded by the sensor.

Abstract: A system includes a plurality of collector devices that are disposed to collect statistical information on packets that are sent between nodes on a network. The system also includes a stackable aggregator that receives network data from the plurality of collector devices, and which produces a connection table that maps each node on the network to a record that stores information about traffic to or from the node. The stackable aggregator includes a manager blade, a database blade, and two or more, analyzer blades.

Abstract: A system for detecting network intrusions and other conditions in a network is described. The system includes a plurality of collector devices that are disposed to collect data and statistical information on packets that are sent between nodes on a network. An aggregator device is disposed to receive data and statistical information from the plurality of collector devices. The aggregator device produces a connection table that maps each node on the network to a record that stores information about traffic to or from the node. The aggregator runs processes that determine network events from aggregating of anomalies into network events.

Abstract: The data protection management apparatus protects digital licenses and digital data, so that the abuse and illegal use of digital data is prevented. The apparatus has an I/O port, session manager, license management engine, usage rules administrator, encryption engine, memory manager, and memory. The license management engine acquires, stores, and manages licenses in sessions opened by the session manager, and the usage rules administrator provides an encryption algorithm and protocol for securely storing and sending digital license data by applying the usage rules to the use of licenses managed by the license management engine.

Abstract: An apparatus for transmitting sound in a motor vehicle including a housing (1) with an inside partition (2), which together define or delimit two separate subspaces (3, 4), which in turn are separated by a transmission valve (6) which opens through the partition (2) and can pivot about a pivot axis (5). The first subspace (3) is connected to an intake manifold of an internal combustion engine, and the second subspace (4) is connected to an interior of the motor vehicle. An elastic and at least partially perforated sealing element (8) is provided in a gap (25) between a peripheral edge (7) of the transmission valve (6) and the housing (1).

Abstract: A receiver that selectively samples a received signal in order to suppress an interference component of the signal while recovering a desired component. The selective sampling may be accomplished by low cost, low complex analog or digital circuitry. The receiver includes a first input that receives a first signal, including a desired signal component and an interference signal component and a second input that receives a second signal including the interference component only. The first and second signals are then provided to the sampling circuitry. First, the phase of the interference component of the both the first and second signals is aligned. Next, the points in a wave cycle that the second signal is at a power minimum are detected. Finally, first signal is sampled close to the point when the second signal is at the power minimum to recover the desired signal component and suppress the interference component.

Abstract: The invention concerns an intermediate layer (2) for enhancing comfort of a user wearing usual objects on or in the body. The intermediate layer comprises at least an element consisting of a heat-sensitive gel having a lower critical solution temperature (LCST). Under the influence of the user's body or skin temperature (T), the intermediate layer actively produces a constant modification of the contact point(s) between the usual object and the user's body (3).

Abstract: A system for detecting network intrusions and other conditions in a network is described. The system includes a plurality of collector devices that are disposed to collect data and statistical information on packets that are sent between nodes on a network. An aggregator device is disposed to receive data and statistical information from the plurality of collector devices. The aggregator device produces a connection table that maps each node on the network to a record that stores information about traffic to or from the node. The aggregator runs processes that determine network events from aggregating of anomalies into network events.

Abstract: Based on a result of determination made by a conflict determination section 13, a resource access section 11 determines whether an application is allowed to access a resource section 16 or not. If access is allowed, a function for realizing access to the resource section 16, which is already registered in the resource access section 11, is called. Thus, it is possible to create applications without paying attention to prevention of resource conflicts. Moreover, the resource section 16 can be reused easily. Furthermore, the entire system can undergo a well-balanced operation.