Patents by Inventor Daniel Willis

Daniel Willis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250390511
    Abstract: A method is disclosed for ingesting and tagging data relating to data elements within a datastore based on features other than merely a word or contiguous words. The data elements are identified within the datastore according to a location of the identified data element, the associated tag, and an aspect of the tagged data element is stored within another datastore. At least one of the location, associated tag, and the aspect of the data is indexed.
    Type: Application
    Filed: August 18, 2024
    Publication date: December 25, 2025
    Inventors: Mark Hedley, Daniel Willis, John Craig, Peter Fong, Helge Brueggemann, Ronnie Jensen
  • Publication number: 20250384489
    Abstract: A method is disclosed for analysing a data set to determine a first processes. Common elements within the data are identified and associated with the first processes. The common elements are mapped within the first processes to provide an estimated process flow for the first process. Another process is evaluated to determine an absence of one or more common elements common to the estimated process flow. A map is then provided of the process flow indicating events and documents forming the similar processes.
    Type: Application
    Filed: January 17, 2025
    Publication date: December 18, 2025
    Inventors: Daniel Willis, Helge Brueggemann, Mark Hedley, Ronnie Jensen
  • Publication number: 20250384376
    Abstract: A method is disclosed for analysing a data set to determine a first processes. Common elements within the data are identified and associated with the first processes. The common elements are mapped within the first processes to provide an estimated process flow for the first process. Another process is evaluated to determine an absence of one or more common elements common to the estimated process flow. A map is then provided of the process flow indicating events and documents forming the similar processes.
    Type: Application
    Filed: January 17, 2025
    Publication date: December 18, 2025
    Inventors: Daniel Willis, Mark Hedley, Helge Brueggemann, Ronnie Jensen, John Craig, Peter Fong, Shawn Kelly Gardner, Yvonne Leonard
  • Publication number: 20250355950
    Abstract: A method is disclosed for analysing a data set to determine a first processes. First messages are provided, the first messages classified into a plurality of different classes with a plurality of different likelihoods, a single first message classified into different classes based on different criteria. From the first messages a first subset of the first messages is retrieved based on a combination of one or more classifications, a likelihood of the one or more classifications, and another classification for messages within the first subset of the first messages. The likelihood of the classifications has more than two (2) potential values.
    Type: Application
    Filed: April 9, 2025
    Publication date: November 20, 2025
    Inventors: Daniel Willis, Mark Hedley, Helge Brueggemann, Ronnie Jensen, Shawn Kelly Gardner, John Craig, Peter Fong
  • Patent number: 11998626
    Abstract: A non-antimicrobial cleansing composition is disclosed comprising from about 10.0 wt. % to less than about 40 wt. % of one or more C1-C8 alcohols; about 0.5 wt. % to about 10.0 wt. % of at least one primary surfactant; 0 wt. % to about 10.0 wt. % of at least one secondary surfactant, with the primary and secondary surfactants having an HLB value greater than 8; a pH adjusting agent; and water. The composition does not achieve a microbial kill level greater than 2.0 log.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: June 4, 2024
    Assignee: GOJO Industries, Inc.
    Inventors: Amanda Jo Copeland, Venkatesan Padyachi, James Bingham, Nick Ciavarella, Kayla Elise Ivey, Carey Jaros, Daniel Willis, Jessica Rae Tittl, Srini Venkatesh
  • Patent number: 11756941
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of dies on a package substrate, and a plurality of smart dies on the package substrate, where the plurality of smart dies include a plurality of interconnects and a plurality of capacitors. The semiconductor package also includes a plurality of routing lines coupled to the dies and the smart dies, where the routing lines are communicatively coupled to the interconnects of the smart dies, where each of the dies has at least two or more routing lines to communicatively couple the dies together, and where one of the routing lines is via the interconnects of the smart dies. The capacitors may be a plurality of metal-insulator-metal (MIM) capacitors. The dies may be a plurality of active dies. The routing lines may communicatively couple first and second active dies to first and second smart dies.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: John Fallin, Daniel Willis
  • Publication number: 20230248625
    Abstract: A non-antimicrobial cleansing composition is disclosed comprising from about 10.0 wt. % to less than about 40 wt. % of one or more C1-C8 alcohols; about 0.5 wt. % to about 10.0 wt. % of at least one primary surfactant; 0 wt. % to about 10.0 wt. % of at least one secondary surfactant, with the primary and secondary surfactants having an HLB value greater than 8; a pH adjusting agent; and water. The composition does not achieve a microbial kill level greater than 2.0 log.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Amanda Jo Copeland, Venkatesan Padyachi, James Bingham, Nick Ciavarella, Kayla Elise Ivey, Carey Jaros, Daniel Willis, Jessica Rae Tittl, Srini Venkatesh
  • Patent number: 11660258
    Abstract: A non-antimicrobial cleansing composition is disclosed comprising from about 10.0 wt. % to less than about 40 wt. % of one or more C1-C8 alcohols; about 0.5 wt. % to about 10.0 wt. % of at least one primary surfactant; 0 wt. % to about 10.0 wt. % of at least one secondary surfactant, with the primary and secondary surfactants having an HLB value greater than 8; a pH adjusting agent; and water. The composition does not achieve a microbial kill level greater than 2.0 log.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: May 30, 2023
    Assignee: GOJO Industries, Inc.
    Inventors: Amanda Jo Copeland, Venkatesan Padyachi, James Bingham, Nick Ciavarella, Kayla Elise Ivey, Carey Jaros, Daniel Willis, Jessica Rae Tittl, Srini Venkatesh
  • Patent number: 11633334
    Abstract: A non-antimicrobial cleansing composition is disclosed comprising from about 10.0 wt. % to less than about 40 wt. % of one or more C1-C8 alcohols; about 0.5 wt. % to about 10.0 wt. % of at least one primary surfactant; 0 wt. % to about 10.0 wt. % of at least one secondary surfactant, with the primary and secondary surfactants having an HLB value greater than 8; a pH adjusting agent; and water. The composition does not achieve a microbial kill level greater than 2.0 log.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: April 25, 2023
    Assignee: GOJO Industries, Inc.
    Inventors: Amanda Jo Copeland, Venkatesan Padyachi, James Bingham, Nick Ciavarella, Kayla Elise Ivey, Carey Jaros, Daniel Willis, Jessica Rae Tittl, Srini Venkatesh
  • Publication number: 20220079851
    Abstract: A non-antimicrobial cleansing composition is disclosed comprising from about 10.0 wt. % to less than about 40 wt. % of one or more C1-C8 alcohols; about 0.5 wt. % to about 10.0 wt. % of at least one primary surfactant; 0 wt. % to about 10.0 wt. % of at least one secondary surfactant, with the primary and secondary surfactants having an HLB value greater than 8; a pH adjusting agent; and water. The composition does not achieve a microbial kill level greater than 2.0 log.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 17, 2022
    Inventors: Amanda Jo Copeland, Venkatesan Padyachi, James Bingham, Nick Ciavarella, Kayla Elise Ivey, Carey Jaros, Daniel Willis, Jessica Rae Tittl, Srini Venkatesh
  • Publication number: 20220062137
    Abstract: A non-antimicrobial cleansing composition is disclosed comprising from about 10.0 wt. % to less than about 40 wt. % of one or more C1-C8 alcohols; about 0.5 wt. % to about 10.0 wt. % of at least one primary surfactant; 0 wt. % to about 10.0 wt. % of at least one secondary surfactant, with the primary and secondary surfactants having an HLB value greater than 8; a pH adjusting agent; and water. The composition does not achieve a microbial kill level greater than 2.0 log.
    Type: Application
    Filed: October 22, 2021
    Publication date: March 3, 2022
    Inventors: Amanda Jo Copeland, Venkatesan Padyachi, James Bingham, Nick Ciavarella, Kayla Elise Ivey, Carey Jaros, Daniel Willis, Jessica Rae Tittl, Srini Venkatesh
  • Patent number: 11185483
    Abstract: A non-antimicrobial cleansing composition is disclosed comprising from about 10.0 wt. % to less than about 40 wt. % of one or more C1-C8 alcohols; about 0.5 wt. % to about 10.0 wt. % of at least one primary surfactant; 0 wt. % to about 10.0 wt. % of at least one secondary surfactant, with the primary and secondary surfactants having an HLB value greater than 8; a pH adjusting agent; and water. The composition does not achieve a microbial kill level greater than 2.0 log.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: November 30, 2021
    Assignee: GOJO Industries, Inc.
    Inventors: Amanda Jo Copeland, Venkatesan Padyachi, James Bingham, Nick Ciavarella, Kayla Elise Ivey, Carey Jaros, Daniel Willis, Jessica Rae Tittl, Srini Venkatesh
  • Patent number: 11023247
    Abstract: The systems and methods disclosed herein provide an improved processor package to determine a connection type between the package and an external circuit and to optimize processor performance based on the connection type. As a non-limiting example, a processor package consistent with the present disclosure may include a central processing unit (CPU) die and a plurality of pins (including two connection detection pins) to connect the package to a motherboard. The CPU die may include connection determination logic and execution policy logic, implemented via processor code (“p-code”), as well as a more typical processor.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Daniel Willis, Jonathan Thibado, Eugene Nelson
  • Publication number: 20200328195
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of dies on a package substrate, and a plurality of smart dies on the package substrate, where the plurality of smart dies include a plurality of interconnects and a plurality of capacitors. The semiconductor package also includes a plurality of routing lines coupled to the dies and the smart dies, where the routing lines are communicatively coupled to the interconnects of the smart dies, where each of the dies has at least two or more routing lines to communicatively couple the dies together, and where one of the routing lines is via the interconnects of the smart dies. The capacitors may be a plurality of metal-insulator-metal (MIM) capacitors. The dies may be a plurality of active dies. The routing lines may communicatively couple first and second active dies to first and second smart dies.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 15, 2020
    Inventors: John FALLIN, Daniel WILLIS
  • Patent number: 10729010
    Abstract: The present subject matter may include an electronic device. The electronic device may include a motherboard socket body. The motherboard socket body may be adapted to couple with a processor. The motherboard socket body may define an aperture in the motherboard socket body. The electronic device may include a socket insulator. The socket insulator may be coupled with the aperture in the motherboard socket body. The socket insulator may include an insulator body that may be sized and shaped to close the aperture in the motherboard socket body. The socket insulator may be configured to isolate electrical communication in portions of the motherboard socket body.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Daniel Willis, Dan H. Gerbus
  • Publication number: 20190306984
    Abstract: The present subject matter may include an electronic device. The electronic device may include a motherboard socket body. The motherboard socket body may be adapted to couple with a processor. The motherboard socket body may define an aperture in the motherboard socket body. The electronic device may include a socket insulator. The socket insulator may be coupled with the aperture in the motherboard socket body. The socket insulator may include an insulator body that may be sized and shaped to close the aperture in the motherboard socket body. The socket insulator may be configured to isolate electrical communication in portions of the motherboard socket body.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Daniel Willis, Dan H. Gerbus
  • Patent number: 10333860
    Abstract: In accordance with a method a plurality of subscriber systems are provided, the systems being coupled via a Wide Area Network (WAN) and comprising a first subscriber system. The first subscriber system has processing and non-volatile storage and is suitably programmed for providing a subscriber service to a first subscriber. The first system is disposed in an unsecured location, which is associated with the first subscriber. Subsequently, the subscriber service is provided to the first subscriber. Separately, a task is provided to the first subscriber system via the WAN and is executed on the first subscriber system. An activity record for the execution of the task is logged, based on an amount of at least one of the processing and the non-volatile storage consumed on the first subscriber system during execution of the task.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: June 25, 2019
    Assignee: LEONOVUS USA
    Inventors: Daniel Willis, Paul Master, Gordon Campbell, Sean O'Hagan, Derek Noble
  • Patent number: 10212483
    Abstract: In accordance with a method a plurality of subscriber systems are provided, the systems being coupled via a Wide Area Network (WAN) and comprising a first subscriber system. The first subscriber system has processing and non-volatile storage and is suitably programmed for providing a subscriber service to a first subscriber. The first system is disposed in an unsecured location, which is associated with the first subscriber. Subsequently, the subscriber service is provided to the first subscriber. Separately, a task is provided to the first subscriber system via the WAN and is executed on the first subscriber system. An activity record for the execution of the task is logged, based on an amount of at least one of the processing and the non-volatile storage consumed on the first subscriber system during execution of the task.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 19, 2019
    Assignee: LeoNovus Inc.
    Inventors: Daniel Willis, Paul Master, Gordon Campbell, Sean O'Hagan, Derek Noble
  • Publication number: 20190042270
    Abstract: The systems and methods disclosed herein provide an improved processor package to determine a connection type between the package and an external circuit and to optimize processor performance based on the connection type. As a non-limiting example, a processor package consistent with the present disclosure may include a central processing unit (CPU) die and a plurality of pins (including two connection detection pins) to connect the package to a motherboard. The CPU die may include connection determination logic and execution policy logic, implemented via processor code (“p-code”), as well as a more typical processor.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Daniel Willis, Jonathan Thibado, Eugene Nelson
  • Publication number: 20180311128
    Abstract: A non-antimicrobial cleansing composition is disclosed comprising from about 10.0 wt. % to less than about 40 wt. % of one or more C1-C8 alcohols; about 0.5 wt. % to about 10.0 wt. % of at least one primary surfactant; 0 wt. % to about 10.0 wt. % of at least one secondary surfactant, with the primary and secondary surfactants having an HLB value greater than 8; a pH adjusting agent; and water. The composition does not achieve a microbial kill level greater than 2.0 log.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 1, 2018
    Inventors: Amanda Jo Copeland, Venkatesan Padyachi, James Bingham, Nick Ciavarella, Kayla Elise Ivey, Carey Jaros, Daniel Willis, Jessica Rae Tittl, Srini Venkatesh