Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

Abstract: Superconducting nanowire single photon detectors have recently been developed for a wide range of applications, including imaging and communications. An improved detection system is disclosed, whereby the detectors are monolithically integrated on the same chip with Josephson junctions for control and data processing. This enables an enhanced data rate, thereby facilitating several new and improved applications. A preferred embodiment comprises integrated digital processing based on single-flux-quantum pulses. An integrated multilayer fabrication method for manufacturing these integrated detectors is also disclosed. Preferred examples of systems comprising such integrated nanowire photon detectors include a time-correlated single photon counter, a quantum random number generator, an integrated single-photon imaging array, a sensitive digital communication receiver, and quantum-key distribution for a quantum communication system.

Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 ?A/?m2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 ?A/?m2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

Abstract: Superconducting nanowire single photon detectors have recently been developed for a wide range of applications, including imaging and communications. An improved detection system is disclosed, whereby the detectors are monolithically integrated on the same chip with Josephson junctions for control and data processing. This enables an enhanced data rate, thereby facilitating several new and improved applications. A preferred embodiment comprises integrated digital processing based on single-flux-quantum pulses. An integrated multilayer fabrication method for manufacturing these integrated detectors is also disclosed. Preferred examples of systems comprising such integrated nanowire photon detectors include a time-correlated single photon counter, a quantum random number generator, an integrated single-photon imaging array, a sensitive digital communication receiver, and quantum-key distribution for a quantum communication system.

Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 ?A/?m2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

Abstract: Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 ?A/?m2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

Abstract: The technology disclosed in this patent document can be implemented to combine quantum computing, classical qubit control/readout, and classical digital computing in a scalable computing system based on superconducting qubits and special interconnection designs for connecting hardware components within a multi-stage cryogenic system to provide fast communications between the quantum computing module and its controller while allowing efficient management of wiring with other modules.

Abstract: Superconducting nanowire single photon detectors have recently been developed for a wide range of applications, including imaging and communications. An improved detection system is disclosed, whereby the detectors are monolithically integrated on the same chip with Josephson junctions for control and data processing. This enables an enhanced data rate, thereby facilitating several new and improved applications. A preferred embodiment comprises integrated digital processing based on single-flux-quantum pulses. An integrated multilayer fabrication method for manufacturing these integrated detectors is also disclosed. Preferred examples of systems comprising such integrated nanowire photon detectors include a time-correlated single photon counter, a quantum random number generator, an integrated single-photon imaging array, a sensitive digital communication receiver, and quantum-key distribution for a quantum communication system.

Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

Abstract: Angiotensin (1-7) analogs are provided. Also provided are methods of making such analogs methods for using analogs as therapeutic compositions such as, for example, treatment cancer.

Abstract: Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes.

Abstract: Provided herein are compounds of Formula I and Formula II, and compositions comprising the same, as well as methods of use thereof for treating kidney stones (e.g., inhibiting the formation of oxalate kidney stones; treating primary hyperoxaluria), inhibiting the production of glyoxylate and/or oxalate, and/or inhibiting glycolate oxidase (GO).

Abstract: Provided herein are methods of treatment for kidney stones, e.g., for controlling or inhibiting the formation of calcium oxalate kidney stones by inhibiting the production of glyoxylate and/or oxalate, treatment of primary hyperoxaluria, etc. In some embodiments, methods comprise administering to a subject in need thereof, in combination, an inhibitor of hydroxyproline dehydrogenase (HYPDH), an inhibitor of glycolate oxidase (GO), and/or another agent for the treatment of kidney stones. Compositions for such use or the use of active agents in the manufacture of a medicament for the treatment of kidney stones are also provided.

Abstract: The present invention relates to compounds that modulate nicotinic receptors as non-competitive antagonists, methods for use, and their pharmaceutical compositions.

Abstract: A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

Abstract: Provided herein are compounds of Formula (I), Formula (II), and Formula (III), and compositions comprising the same, as well as methods of use thereof for controlling or inhibiting the formation of calcium oxalate kidney stones, inhibiting the production of glyoxylate and/or oxalate, and/or inhibiting hydroxyproline dehydrogenase (HYPDH).