Abstract: An amplifier (100) comprising: first, second, third and fourth transistors (M1, M2, M3, M4), an input (10) for an input signal, and a first output (22) for a first amplified signal; a first terminal (T11) of the first transistor (M1) coupled to a first voltage rail (12), a second terminal (T12) of the first transistor (M1) coupled to a first terminal (T31) of the third transistor (M3), and a gate (G1) of the first transistor (M1) coupled to the input (10); a first terminal (T21) of the second transistor (M2) coupled to a second voltage rail (14), a second terminal (T22) of the second transistor (M2) coupled to the first output (22), and a gate (G2) of the second transistor (M2) coupled to the input (10); a load (40) coupled between a second terminal (T32) of the third transistor (M3) and a third voltage rail (20), and a gate (G3) of the third transistor (M3) coupled to a bias node (16) for applying a bias voltage to the gate (G3) of the third transistor (M3); a first terminal (T41) of the fourth transistor

Abstract: An amplifier (100) comprising: first, second, third and fourth transistors (M1, M2, M3, M4), an input (10) for an input signal, and a first output (22) for a first amplified signal; a first terminal (T11) of the first transistor (M1) coupled to a first voltage rail (12), a second terminal (T12) of the first transistor (M1) coupled to a first terminal (T31) of the third transistor (M3), and a gate (G1) of the first transistor (M1) coupled to the input (10); a first terminal (T21) of the second transistor (M2) coupled to a second voltage rail (14), a second terminal (T22) of the second transistor (M2) coupled to the first output (22), and a gate (G2) of the second transistor (M2) coupled to the input (10); a load (40) coupled between a second terminal (T32) of the third transistor (M3) and a third voltage rail (20), and a gate (G3) of the third transistor (M3) coupled to a bias node (16) for applying a bias voltage to the gate (G3) of the third transistor (M3); a first terminal (T41) of the fourth transistor

Abstract: In a passive mixer, switches and a capacitance are shared between bootstrapped mixing transistors, reducing the number of components required as compared to prior art bootstrap designs. Shared bootstrap circuits operate in an interleaved fashion between I and Q mixer circuits, at twice the LO frequency. That is, the shared bootstrap circuits in each I mixer circuit charge their capacitors in a first half-period of a clock, and connect the shared capacitor to the gate of an enabled mixing transistor in the second half-period. The shared bootstrap circuits in the Q mixer circuit charge their capacitors in the second half-period, and connect the shared capacitor to the gate of an enabled mixing transistor in the first half-period. One of two mixing transistors connected to each shared bootstrap circuit is alternately enabled during the clock signal half-periods that the shared bootstrap circuit is not charging its capacitor.

Abstract: In a time-interleaved Analog to Digital Converter, circuit components and capacitances may be shared among a plurality of sample and hold circuits in each of two sets. The two shared circuits alternate, on different half-periods of a master clock signal, between charging a capacitance and sampling an input in an overlapping manner such that one is charging while the other is sampling. One sample and hold circuit is activated during each successive half-period (following a charging half-period) by independent, sequential, non-overlapping clocking signals. To improve SNDR, at least one switch is bootstrapped by driving its gate terminal with the voltage of a capacitor configured between the gate and the input signal. By sharing at least some components among multiple sample and hold circuits, the number of gates driven by clock signals is reduced, reducing clock distribution and calibration complexity, and the circuit area is reduced.

Abstract: An attenuator control method of a signal processing chain comprising two or more signal processing units is disclosed. One of the two or more signal processing units is a signal attenuator adapted to apply adaptive signal attenuation of an attenuator input signal based on one or more attenuation parameters to provide an attenuator output signal. At least one of the two or more signal processing units has an associated wearout process and a corresponding wearout budget, wherein a wearout event of the wearout process occurs when a level of a wearout indication signal of the signal processing chain is in a wearout region, and wherein the wearout process is modeled by a wearout event cost associated with a corresponding wearout event. The method comprises obtaining an indication of whether a wearout event of the wearout process has occurred.

Abstract: The present disclosure generally relates to the field of receiver structures in radio communication systems and more specifically to passive mixers in the receiver structure and to a technique for converting a first signal having a first frequency into a second signal having a second frequency by using a third signal having a third frequency.